706e71076e
Some of the tests from the X86 directory can be generalized to improve coverage for other architectures
37 lines
1.8 KiB
LLVM
37 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: %if x86-registered-target %{ opt -passes=slp-vectorizer -S -slp-threshold=-10 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s %}
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; RUN: %if aarch64-registered-target %{ opt -passes=slp-vectorizer -S -slp-threshold=-10 -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s %}
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define void @test(i8 %0) {
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; CHECK-LABEL: define void @test(
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; CHECK-SAME: i8 [[TMP0:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP1:%.*]] = insertelement <2 x i8> <i8 0, i8 poison>, i8 [[TMP0]], i32 1
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; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i8> [[TMP1]] to <2 x i32>
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; CHECK-NEXT: [[TMP3:%.*]] = mul <2 x i8> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x i8> [[TMP3]], i32 0
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; CHECK-NEXT: [[TMP5:%.*]] = zext i8 [[TMP4]] to i32
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i8> [[TMP3]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = zext i8 [[TMP6]] to i32
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; CHECK-NEXT: [[ADD:%.*]] = or i32 [[TMP5]], [[TMP7]]
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; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[ADD]], 1
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; CHECK-NEXT: [[CONV9:%.*]] = trunc i32 [[SHR]] to i8
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; CHECK-NEXT: store i8 [[CONV9]], ptr null, align 1
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; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <8 x i32> <i32 1, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
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; CHECK-NEXT: ret void
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;
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entry:
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%conv3 = sext i8 %0 to i32
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%conv7 = sext i8 0 to i32
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%conv = zext i16 0 to i32
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%mul = mul i32 %conv3, %conv
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%conv6 = zext i16 0 to i32
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%mul8 = mul i32 %conv7, %conv6
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%add = or i32 %mul8, %mul
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%shr = lshr i32 %add, 1
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%conv9 = trunc i32 %shr to i8
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store i8 %conv9, ptr null, align 1
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%broadcast.splatinsert = insertelement <8 x i32> poison, i32 %conv3, i64 0
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ret void
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}
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