4f7e5d2206
Currently, SROA is CFG-preserving. Not doing so does not affect any pipeline test. (???) Internally, SROA requires Dominator Tree, and uses it solely for the final `-mem2reg` call. By design, we can't really SROA alloca if their address escapes somehow, but we have logic to deal with `load` of `select`/`PHI`, where at least one of the possible addresses prevents promotion, by speculating the `load`s and `select`ing between loaded values. As one would expect, that requires ensuring that the speculation is actually legal. Even ignoring complexity bailouts, that logic does not deal with everything, e.g. `isSafeToLoadUnconditionally()` does not recurse into hands of `select`. There can also be cases where the load is genuinely non-speculate. So if we can't prove that the load can be speculated, unfold the select, produce two-entry phi node, and perform predicated load. Now, that transformation must obviously update Dominator Tree, since we require it later on. Doing so is trivial. Additionally, we don't want to do this for the final SROA invocation (D136806). In the end, this ends up having negative (!) compile-time cost: https://llvm-compile-time-tracker.com/compare.php?from=c6d7e80ec4c17a415673b1cfd25924f98ac83608&to=ddf9600365093ea50d7e278696cbfa01641c959d&stat=instructions:u Though indeed, this only deals with `select`s, `PHI`s are still using speculation. Should we update some more analysis? Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D138238 This reverts commit 739611870d3b06605afe25cc07833f6a62de9545, and recommits 03e6d9d9d1d48e43f3efc35eb75369b90d4510d5 with a fixed assertion - we should check that DTU is there, not just assert false...
138 lines
4.8 KiB
LLVM
138 lines
4.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes='sroa<preserve-cfg>' -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PRESERVE-CFG
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; RUN: opt -passes='sroa<modify-cfg>' -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-MODIFY-CFG
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; This test checks that SROA does not introduce ptrtoint and inttoptr
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; casts from and to non-integral pointers. The "ni:4" bit in the
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; datalayout states that pointers of address space 4 are to be
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; considered "non-integral".
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4"
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target triple = "x86_64-unknown-linux-gnu"
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define void @f0(i1 %alwaysFalse, i64 %val) {
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; CHECK-LABEL: @f0(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LOC:%.*]] = alloca i64, align 8
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; CHECK-NEXT: store i64 [[VAL:%.*]], ptr [[LOC]], align 8
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; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
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; CHECK: neverTaken:
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; CHECK-NEXT: [[LOC_0_PTR:%.*]] = load ptr addrspace(4), ptr [[LOC]], align 8
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; CHECK-NEXT: store i8 5, ptr addrspace(4) [[LOC_0_PTR]], align 1
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; CHECK-NEXT: ret void
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; CHECK: alwaysTaken:
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; CHECK-NEXT: ret void
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;
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entry:
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%loc = alloca i64
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store i64 %val, ptr %loc
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br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
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neverTaken:
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%ptr = load ptr addrspace(4), ptr %loc
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store i8 5, ptr addrspace(4) %ptr
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ret void
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alwaysTaken:
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ret void
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}
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define i64 @f1(i1 %alwaysFalse, ptr addrspace(4) %val) {
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; CHECK-LABEL: @f1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LOC:%.*]] = alloca ptr addrspace(4), align 8
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; CHECK-NEXT: store ptr addrspace(4) [[VAL:%.*]], ptr [[LOC]], align 8
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; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
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; CHECK: neverTaken:
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; CHECK-NEXT: [[LOC_0_INT:%.*]] = load i64, ptr [[LOC]], align 8
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; CHECK-NEXT: ret i64 [[LOC_0_INT]]
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; CHECK: alwaysTaken:
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; CHECK-NEXT: ret i64 42
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;
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entry:
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%loc = alloca ptr addrspace(4)
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store ptr addrspace(4) %val, ptr %loc
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br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
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neverTaken:
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%int = load i64, ptr %loc
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ret i64 %int
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alwaysTaken:
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ret i64 42
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}
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define ptr addrspace(4) @memset(i1 %alwaysFalse) {
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; CHECK-LABEL: @memset(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = alloca ptr addrspace(4), align 8
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; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[X]], i8 5, i64 8, i1 false)
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; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
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; CHECK: neverTaken:
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; CHECK-NEXT: [[X_0_X_FIELD_LD_0:%.*]] = load ptr addrspace(4), ptr [[X]], align 8
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; CHECK-NEXT: ret ptr addrspace(4) [[X_0_X_FIELD_LD_0]]
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; CHECK: alwaysTaken:
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; CHECK-NEXT: ret ptr addrspace(4) null
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;
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entry:
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%x = alloca ptr addrspace(4)
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call void @llvm.memset.p0.i64(ptr align 8 %x, i8 5, i64 16, i1 false)
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br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
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neverTaken:
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%x.field.ld.0 = load ptr addrspace(4), ptr %x
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ret ptr addrspace(4) %x.field.ld.0
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alwaysTaken:
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ret ptr addrspace(4) null
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}
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;; TODO: This one demonstrates a missed oppurtunity. The only known bit
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;; pattern for a non-integral bit pattern is that null is zero. As such
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;; we could do SROA and replace the memset w/a null store. This will
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;; usually be gotten by instcombine.
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define ptr addrspace(4) @memset_null(i1 %alwaysFalse) {
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; CHECK-LABEL: @memset_null(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[X:%.*]] = alloca ptr addrspace(4), align 8
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; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[X]], i8 0, i64 8, i1 false)
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; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
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; CHECK: neverTaken:
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; CHECK-NEXT: [[X_0_X_FIELD_LD_0:%.*]] = load ptr addrspace(4), ptr [[X]], align 8
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; CHECK-NEXT: ret ptr addrspace(4) [[X_0_X_FIELD_LD_0]]
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; CHECK: alwaysTaken:
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; CHECK-NEXT: ret ptr addrspace(4) null
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;
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entry:
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%x = alloca ptr addrspace(4)
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call void @llvm.memset.p0.i64(ptr align 8 %x, i8 0, i64 16, i1 false)
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br i1 %alwaysFalse, label %neverTaken, label %alwaysTaken
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neverTaken:
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%x.field.ld.0 = load ptr addrspace(4), ptr %x
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ret ptr addrspace(4) %x.field.ld.0
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alwaysTaken:
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ret ptr addrspace(4) null
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}
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%union.anon = type { ptr }
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define ptr@f2(ptr addrspace(4) %p) {
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; CHECK-LABEL: @f2(
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; CHECK-NEXT: [[DOTSROA_0:%.*]] = alloca ptr, align 8
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; CHECK-NEXT: store ptr addrspace(4) [[P:%.*]], ptr [[DOTSROA_0]], align 8
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; CHECK-NEXT: [[DOTSROA_0_0__SROA_0_0_:%.*]] = load ptr, ptr [[DOTSROA_0]], align 8
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; CHECK-NEXT: ret ptr [[DOTSROA_0_0__SROA_0_0_]]
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;
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%1 = alloca %union.anon, align 8
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store ptr addrspace(4) %p, ptr %1, align 8
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%2 = load ptr, ptr %1, align 8
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ret ptr %2
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}
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declare void @llvm.memset.p0.i64(ptr, i8, i64, i1)
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK-MODIFY-CFG: {{.*}}
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; CHECK-PRESERVE-CFG: {{.*}}
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