ee13638362
Since e39f6c1844fab59c638d8059a6cf139adb42279a opt will infer the correct datalayout when given a triple. Avoid explicitly specifying it in tests that depend on the AMDGPU target being present to avoid the string becoming out of sync with the TargetInfo value. Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg were updated to ensure that tests for non-target-specific passes that happen to use the AMDGPU layout still pass when building with a limited set of targets. Reviewed By: shiltian, arsenm Pull Request: https://github.com/llvm/llvm-project/pull/137921
33 lines
1.2 KiB
LLVM
33 lines
1.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
|
; RUN: opt < %s -passes=vector-combine -S -mtriple=amdgcn-amd-amdhsa | FileCheck %s --check-prefixes=CHECK
|
|
|
|
; ModuleID = 'load-as-transition.ll'
|
|
target triple = "amdgcn-amd-amdhsa"
|
|
|
|
%struct.hoge = type { float }
|
|
|
|
define protected amdgpu_kernel void @load_from_other_as(ptr nocapture nonnull %resultptr) local_unnamed_addr #0 {
|
|
; CHECK-LABEL: @load_from_other_as(
|
|
; CHECK-NEXT: bb:
|
|
; CHECK-NEXT: [[A:%.*]] = alloca [[STRUCT_HOGE:%.*]], align 4, addrspace(5)
|
|
; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(5) [[A]] to ptr
|
|
; CHECK-NEXT: [[D:%.*]] = load float, ptr [[TMP0]], align 4
|
|
; CHECK-NEXT: [[E:%.*]] = insertelement <4 x float> undef, float [[D]], i32 0
|
|
; CHECK-NEXT: store <4 x float> [[E]], ptr [[RESULTPTR:%.*]], align 16
|
|
; CHECK-NEXT: ret void
|
|
;
|
|
bb:
|
|
%a = alloca %struct.hoge, align 4, addrspace(5)
|
|
%b = addrspacecast ptr addrspace(5) %a to ptr
|
|
%d = load float, ptr %b, align 4
|
|
%e = insertelement <4 x float> undef, float %d, i32 0
|
|
store <4 x float> %e, ptr %resultptr, align 16
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "use-soft-float"="false" }
|
|
|
|
!llvm.ident = !{!0}
|
|
|
|
!0 = !{!"clang version 12.0.0"}
|