llvm-project

History

[RISCV] Add TunePreferAscendingLoadStore for SpacemiT X60 LD/ST fusion (#186967 )

Add a tune feature that reverses the callee-saved register spill/restore
order so that addresses are ascending, enabling LD/ST fusion on
processors like SpacemiT X60.

Co-authored-by: LiqinWeng <liqin.weng@spacemit.com>
Co-authored-by: Claude Opus 4.6 <noreply@anthropic.com>

2026-03-26 14:02:11 +08:00

CMakeLists.txt

[RISCV] Split code that tablegen needs out of RISCVISAInfo. (#89684 )

2024-04-23 15:12:36 -07:00

CSKYTargetParserTest.cpp

[llvm] Use llvm::erase_if (NFC) (#141185 )

2025-05-23 10:32:58 -07:00

Host.cpp

[NFC] Fix unused but set variable

2026-01-28 00:25:22 -04:00

RISCVISAInfoTest.cpp

[RISCV] Update P extension to 0.21 (#188121 )