9f422915c7
This PR re-lands https://github.com/llvm/llvm-project/pull/156830 This PR aims at fixing the nvdsl examples which got a bit out of sync not being tested in the CI. The fixed bugs were related to the following PRs: - move to nanobind #118583 - split gpu module initialization #135478 - gpu dialect python API change #163883
135 lines
6.6 KiB
Python
135 lines
6.6 KiB
Python
# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \
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# RUN: sh -c 'if [[ "%mlir_run_cuda_sm90_tests" == "1" ]]; \
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# RUN: then %PYTHON %s | FileCheck %s; \
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# RUN: else export MLIR_NVDSL_PRINT_IR=1; \
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# RUN: %PYTHON %s | FileCheck %s --check-prefix=DUMPIR; fi'
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# ===----------------------------------------------------------------------===//
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# Chapter 2 : 2D Saxpy with TMA
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# ===----------------------------------------------------------------------===//
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#
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# This program demonstrates 2D Saxpy. It is same as Chapter 1,
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# but it loads data using TMA (Tensor Memory Accelerator)
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#
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# This chapter introduces demonstrates:
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# 1. Computes 2D SAXPY in the same way as Ch1.py but loads data using TMA
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# 2. Create and initialize 1 asynchronous transactional barrier (mbarrier)
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# 3. Thread-0 Load request data load from TMA for each thread block
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# 4. Each thread block loads <1x32xf32> for x and y.
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# 5. Wait for completion of TMA load with mbarrier
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#
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# ===----------------------------------------------------------------------===//
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from mlir import ir
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from mlir.dialects import nvgpu, scf, arith, memref, vector, gpu
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from tools.nvdsl import *
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from mlir import runtime as rt
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from mlir.extras import types as T
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import numpy as np
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@NVDSL.mlir_func
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def saxpy(x, y, alpha):
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token_ty = gpu.AsyncTokenType.get()
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t1 = gpu.wait([])
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x_dev, t2 = gpu.alloc(x.type, token_ty, [t1], [], [])
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y_dev, t3 = gpu.alloc(y.type, token_ty, [t2], [], [])
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t4 = gpu.memcpy(token_ty, [t3], x_dev, x)
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t5 = gpu.memcpy(token_ty, [t4], y_dev, y)
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t6 = gpu.wait([t5])
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x_tma = TMA([1, N], x.type)
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y_tma = TMA([1, N], y.type)
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x_tma.create_descriptor(x_dev)
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y_tma.create_descriptor(y_dev)
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sz_x = get_type_size(x_tma.tma_memref)
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sz_y = get_type_size(x_tma.tma_memref)
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sz = sz_x + sz_y
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@NVDSL.mlir_gpu_launch(grid=(M, 1, 1), block=(N, 1, 1), smem=sz)
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def saxpy_tma_kernel():
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bidx = gpu.block_id(gpu.Dimension.x)
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tidx = gpu.thread_id(gpu.Dimension.x)
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isThread0 = tidx == 0
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# 1. Create and initialize asynchronous transactional barrier (mbarrier)
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mbar_group = Mbarriers(number_of_barriers=1)
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mbar_group[0].init(1, predicate=isThread0)
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# 2. Execute Tensor Memory Accelerator (TMA) Load
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x_smem = get_dynamic_shared_memory([1, N], T.f32())
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y_smem = get_dynamic_shared_memory([1, N], T.f32(), offset=sz_x)
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x_tma.load(x_smem, mbar_group[0], coords=[0, bidx], predicate=isThread0)
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y_tma.load(y_smem, mbar_group[0], coords=[0, bidx], predicate=isThread0)
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mbar_group[0].arrive(txcount=sz, predicate=isThread0)
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# 3. Wait for completion of TMA load with mbarrier
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mbar_group[0].try_wait()
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x_val = memref.load(x_smem, [const(0), tidx])
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y_val = memref.load(y_smem, [const(0), tidx])
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# SAXPY: y[i] += a * x[i];
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y_val += x_val * alpha
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memref.store(y_val, y_dev, [bidx, tidx])
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saxpy_tma_kernel()
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t7 = gpu.memcpy(token_ty, [t6], y, y_dev)
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gpu.wait([t7])
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# 3. Pass numpy arrays to MLIR
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M = 256
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N = 32
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alpha = 2.0
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x = np.random.randn(M, N).astype(np.float32)
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y = np.ones((M, N), np.float32)
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saxpy(x, y, alpha)
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if os.getenv("MLIR_NVDSL_PRINT_IR") != "1":
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# 4. Verify MLIR with reference computation
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ref = np.ones((M, N), np.float32)
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ref += x * alpha
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np.testing.assert_allclose(y, ref, rtol=5e-03, atol=1e-01)
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print("PASS")
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# CHECK-NOT: Mismatched elements
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# CHECK: PASS
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# DUMPIR: func.func @saxpy(%{{.*}}: memref<256x32xf32>, %[[ARG1:.*]]: memref<256x32xf32>, %[[ARG2:.*]]: f32) attributes {llvm.emit_c_interface} {
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# DUMPIR: %[[WAIT0:.*]] = gpu.wait async
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# DUMPIR: %[[MEMREF:.*]], %[[ASYNC0:.*]] = gpu.alloc async [%[[WAIT0]]] () : memref<256x32xf32>
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# DUMPIR: %[[CAST:.*]] = memref.cast %[[MEMREF]] : memref<256x32xf32> to memref<*xf32>
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# DUMPIR: %[[C1:.*]] = arith.constant 1 : index
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# DUMPIR: %[[C32:.*]] = arith.constant 32 : index
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# DUMPIR: %[[TMA0:.*]] = nvgpu.tma.create.descriptor %[[CAST]] box[%[[C1]], %[[C32]]] : memref<*xf32> -> <tensor = memref<1x32xf32, 3>, swizzle = none, l2promo = none, oob = zero, interleave = none>
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# DUMPIR: %[[C0:.*]] = arith.constant 0 : index
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# DUMPIR: %[[EQ:.*]] = arith.cmpi eq, %{{.*}}, %[[C0]] : index
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# DUMPIR: %[[MB:.*]] = nvgpu.mbarrier.create -> <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_10:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C1_11:.*]] = arith.constant 1 : index
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# DUMPIR: nvgpu.mbarrier.init %[[MB]][%[[C0_10]]], %[[C1_11]], predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[DSM0:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_12:.*]] = arith.constant 0 : index
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# DUMPIR: %[[VIEW:.*]] = memref.view %[[DSM0]][%[[C0_12]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<1x32xf32, #gpu.address_space<workgroup>>
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# DUMPIR: %[[DSM1:.*]] = gpu.dynamic_shared_memory : memref<?xi8, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C128:.*]] = arith.constant 128 : index
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# DUMPIR: %[[VIEW_13:.*]] = memref.view %[[DSM1]][%[[C128]]][] : memref<?xi8, #gpu.address_space<workgroup>> to memref<1x32xf32, #gpu.address_space<workgroup>>
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# DUMPIR: nvgpu.tma.async.load %[[TMA0]][%{{.*}}, %{{.*}}], %[[MB]][%{{.*}}] to %[[VIEW]], predicate = %[[EQ]] : <tensor = memref<1x32xf32, 3>, swizzle = none, l2promo = none, oob = zero, interleave = none>, <memorySpace = #gpu.address_space<workgroup>> -> memref<1x32xf32, #gpu.address_space<workgroup>>
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# DUMPIR: nvgpu.mbarrier.arrive.expect_tx %[[MB]][%{{.*}}], %{{.*}}, predicate = %[[EQ]] : <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_20:.*]] = arith.constant 0 : index
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# DUMPIR: %[[C10000000:.*]] = arith.constant 10000000 : index
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# DUMPIR: %[[FALSE:.*]] = arith.constant false
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# DUMPIR: nvgpu.mbarrier.try_wait.parity %[[MB]][%[[C0_20]]], %[[FALSE]], %[[C10000000]] : <memorySpace = #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_21:.*]] = arith.constant 0 : index
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# DUMPIR: %[[LD0:.*]] = memref.load %[[VIEW]][%[[C0_21]], %{{.*}}] : memref<1x32xf32, #gpu.address_space<workgroup>>
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# DUMPIR: %[[C0_22:.*]] = arith.constant 0 : index
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# DUMPIR: %[[LD1:.*]] = memref.load %[[VIEW_13]][%[[C0_22]], %{{.*}}] : memref<1x32xf32, #gpu.address_space<workgroup>>
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# DUMPIR: memref.store %{{.*}}, %{{.*}}[%{{.*}}, %{{.*}}] : memref<256x32xf32>
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# DUMPIR: %[[MEMCPY3:.*]] = gpu.memcpy async [%{{.*}}] %[[ARG1]], %{{.*}} : memref<256x32xf32>, memref<256x32xf32>
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# DUMPIR: %{{.*}} = gpu.wait async [%[[MEMCPY3]]]
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# DUMPIR: return
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# DUMPIR: }
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