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llvm-project/llvm/test/CodeGen/SPARC
History
Matt Arsenault d151f1be41
SPARC: Add sincos intrinsic test (#147464)
2025-07-09 09:21:46 +09:00
..
32abi.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
64abi.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
64atomics.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
64bit.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
64cond.ll
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64spill.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2006-01-22-BitConvertLegalize.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2007-05-09-JumpTables.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2007-07-05-LiveIntervalAssert.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2008-10-10-InlineAsmMemoryOperand.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2008-10-10-InlineAsmRegOperand.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2009-08-28-PIC.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2009-08-28-WeakLinkage.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2011-01-11-Call.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2011-01-11-CC.ll
[SPARC] Use addxccc to do multiword addition when we have VIS3
2025-04-16 08:36:47 +07:00
2011-01-11-FrameAddr.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2011-01-19-DelaySlot.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
2011-01-21-ByValArgs.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2011-01-22-SRet.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2011-12-03-TailDuplication.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
2012-05-01-LowerArguments.ll
…
2013-05-17-CallFrame.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
alloca-align.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
analyze-branch.ll
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atomicrmw-uinc-udec-wrap.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
atomics.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
basictest.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
bigreturn.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
bitcast.ll
[SPARC] Use native bitcast instructions when we have VIS3
2025-04-17 23:39:46 +07:00
blockaddr.ll
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branches-relax.ll
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branches-v9.ll
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cast-sret-func.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
codemodel.ll
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constpool.ll
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constructor.ll
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ctlz.ll
[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
2025-06-20 05:12:51 +07:00
ctpop.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
cttz.ll
[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
2025-06-20 05:12:51 +07:00
data-align.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
DbgValueOtherTargets.test
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
disable-fsmuld-fmuls.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
empty-functions.ll
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exception.ll
Sparc: Improve SETHI and R_SPARC_DISP32 tests
2025-05-05 09:17:27 -07:00
float-constants.ll
[SPARC] Use op-then-halve instructions when we have VIS3
2025-05-23 22:44:05 +07:00
float-vis3.ll
[SPARC] Use op-then-halve instructions when we have VIS3
2025-05-23 22:44:05 +07:00
float.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
fmuladd-soft-float.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
fp16-promote.ll
[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)
2025-02-19 10:16:57 +01:00
fp128-select.ll
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fp128-split.ll
DAG: Preserve disjoint flag when emitting final instructions (#110795)
2024-10-02 19:37:04 +04:00
fp128.ll
PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)
2025-02-05 23:29:02 +07:00
fshl.ll
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func-addr.ll
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getpcx-call.ll
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getpcx-rdpc.ll
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globals.ll
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hard-quad-float.ll
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imm.ll
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inline-asm-i-constraint-i1.ll
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inlineasm-bad.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
inlineasm-output-template.ll
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inlineasm-v9.ll
[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
2025-06-20 05:12:51 +07:00
inlineasm.ll
[SPARC][IAS] Properly set implied feature sets for ISA levels/extensions (#143232)
2025-06-20 05:12:51 +07:00
leafproc.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
LeonCASAInstructionUT.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
LeonDetectRoundChangePassUT.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
LeonFixAllFDIVSQRTPassUT.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
LeonInsertNOPLoadPassUT.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
LeonItinerariesUT.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
LeonSMACUMACInstructionUT.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
lit.local.cfg
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llvm.sincos.ll
SPARC: Add sincos intrinsic test (#147464)
2025-07-09 09:21:46 +09:00
mature-mc-support.ll
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missing-sret.ll
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missinglabel.ll
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mult-alt-generic-sparc.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
multiple-div.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
multiply-extension.ll
Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (#136475)
2025-04-22 20:57:56 +07:00
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
obj-relocs.ll
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overflow-intrinsic-optimizations.ll
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parts.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
pic.ll
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private.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
readcycle.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
reg64.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
register-clobber.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
rem.ll
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reserved-arg-regs.ll
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reserved-regs-named.ll
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reserved-regs-unavailable.ll
CodeGen: Emit error if getRegisterByName fails (#145194)
2025-06-23 16:33:35 +09:00
reserved-regs.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
salvage-debug-isel.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
select-mask.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
sethiandn.ll
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setjmp.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
smulo-128-legalisation-lowering.ll
Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (#136475)
2025-04-22 20:57:56 +07:00
soft-float.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
soft-mul-div.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
spill.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
spillsize.ll
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sret-secondary.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
stack-align.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
stack-protector.ll
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tailcall.ll
[RegAlloc] Sort CopyHint by IsCSR (#131046)
2025-04-14 09:58:46 -04:00
thread-pointer.ll
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tls.ll
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tn0009.mir
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
tn0010.mir
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
tn0011.ll
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tn0012.mir
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
tn0013.mir
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
trap.ll
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umulo-128-legalisation-lowering.ll
Reapply "[SPARC] Use umulxhi to do extending 64x64->128 multiply when we have VIS3" (#135897) (#136475)
2025-04-22 20:57:56 +07:00
varargs-v8.ll
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varargs.ll
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vector-call.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
vector-extract-elt.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00
zerostructcall.ll
[Sparc,test] Change llc -march= to -mtriple=
2024-12-15 10:29:34 -08:00