109b7d965c
The MCSymbolRefExpr::create overload with the specifier parameter is discouraged and being phased out. Expressions with relocation specifiers should use MCSpecifierExpr instead.
872 lines
28 KiB
C++
872 lines
28 KiB
C++
//===- bolt/Target/RISCV/RISCVMCPlusBuilder.cpp -----------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides RISCV-specific MCPlus builder.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVMCAsmInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "bolt/Core/MCPlusBuilder.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#define DEBUG_TYPE "mcplus"
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using namespace llvm;
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using namespace bolt;
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namespace {
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class RISCVMCPlusBuilder : public MCPlusBuilder {
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public:
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using MCPlusBuilder::MCPlusBuilder;
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bool equals(const MCSpecifierExpr &A, const MCSpecifierExpr &B,
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CompFuncTy Comp) const override {
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const auto &RISCVExprA = cast<MCSpecifierExpr>(A);
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const auto &RISCVExprB = cast<MCSpecifierExpr>(B);
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if (RISCVExprA.getSpecifier() != RISCVExprB.getSpecifier())
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return false;
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return MCPlusBuilder::equals(*RISCVExprA.getSubExpr(),
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*RISCVExprB.getSubExpr(), Comp);
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}
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void getCalleeSavedRegs(BitVector &Regs) const override {
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Regs |= getAliases(RISCV::X2);
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Regs |= getAliases(RISCV::X8);
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Regs |= getAliases(RISCV::X9);
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Regs |= getAliases(RISCV::X18);
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Regs |= getAliases(RISCV::X19);
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Regs |= getAliases(RISCV::X20);
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Regs |= getAliases(RISCV::X21);
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Regs |= getAliases(RISCV::X22);
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Regs |= getAliases(RISCV::X23);
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Regs |= getAliases(RISCV::X24);
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Regs |= getAliases(RISCV::X25);
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Regs |= getAliases(RISCV::X26);
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Regs |= getAliases(RISCV::X27);
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}
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bool shouldRecordCodeRelocation(uint32_t RelType) const override {
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switch (RelType) {
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case ELF::R_RISCV_JAL:
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case ELF::R_RISCV_CALL:
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case ELF::R_RISCV_CALL_PLT:
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case ELF::R_RISCV_BRANCH:
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case ELF::R_RISCV_RVC_BRANCH:
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case ELF::R_RISCV_RVC_JUMP:
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case ELF::R_RISCV_GOT_HI20:
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case ELF::R_RISCV_PCREL_HI20:
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case ELF::R_RISCV_PCREL_LO12_I:
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case ELF::R_RISCV_PCREL_LO12_S:
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case ELF::R_RISCV_HI20:
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case ELF::R_RISCV_LO12_I:
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case ELF::R_RISCV_LO12_S:
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case ELF::R_RISCV_TLS_GOT_HI20:
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case ELF::R_RISCV_TLS_GD_HI20:
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return true;
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default:
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llvm_unreachable("Unexpected RISCV relocation type in code");
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}
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}
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bool isNop(const MCInst &Inst) const {
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return Inst.getOpcode() == RISCV::ADDI &&
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Inst.getOperand(0).getReg() == RISCV::X0 &&
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Inst.getOperand(1).getReg() == RISCV::X0 &&
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Inst.getOperand(2).getImm() == 0;
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}
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bool isCNop(const MCInst &Inst) const {
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return Inst.getOpcode() == RISCV::C_NOP;
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}
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bool isNoop(const MCInst &Inst) const override {
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return isNop(Inst) || isCNop(Inst);
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}
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bool isPseudo(const MCInst &Inst) const override {
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switch (Inst.getOpcode()) {
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default:
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return MCPlusBuilder::isPseudo(Inst);
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case RISCV::PseudoCALL:
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case RISCV::PseudoTAIL:
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return false;
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}
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}
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bool isIndirectCall(const MCInst &Inst) const override {
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if (!isCall(Inst))
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return false;
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::JALR:
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case RISCV::C_JALR:
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case RISCV::C_JR:
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return true;
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}
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}
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bool hasPCRelOperand(const MCInst &Inst) const override {
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::JAL:
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case RISCV::AUIPC:
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return true;
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}
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}
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unsigned getInvertedBranchOpcode(unsigned Opcode) const {
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switch (Opcode) {
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default:
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llvm_unreachable("Failed to invert branch opcode");
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return Opcode;
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case RISCV::BEQ:
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return RISCV::BNE;
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case RISCV::BNE:
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return RISCV::BEQ;
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case RISCV::BLT:
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return RISCV::BGE;
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case RISCV::BGE:
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return RISCV::BLT;
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case RISCV::BLTU:
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return RISCV::BGEU;
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case RISCV::BGEU:
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return RISCV::BLTU;
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case RISCV::C_BEQZ:
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return RISCV::C_BNEZ;
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case RISCV::C_BNEZ:
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return RISCV::C_BEQZ;
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}
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}
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void reverseBranchCondition(MCInst &Inst, const MCSymbol *TBB,
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MCContext *Ctx) const override {
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auto Opcode = getInvertedBranchOpcode(Inst.getOpcode());
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Inst.setOpcode(Opcode);
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replaceBranchTarget(Inst, TBB, Ctx);
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}
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void replaceBranchTarget(MCInst &Inst, const MCSymbol *TBB,
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MCContext *Ctx) const override {
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assert((isCall(Inst) || isBranch(Inst)) && !isIndirectBranch(Inst) &&
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"Invalid instruction");
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unsigned SymOpIndex;
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auto Result = getSymbolRefOperandNum(Inst, SymOpIndex);
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(void)Result;
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assert(Result && "unimplemented branch");
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Inst.getOperand(SymOpIndex) =
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MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx));
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}
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IndirectBranchType analyzeIndirectBranch(
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MCInst &Instruction, InstructionIterator Begin, InstructionIterator End,
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const unsigned PtrSize, MCInst *&MemLocInstr, unsigned &BaseRegNum,
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unsigned &IndexRegNum, int64_t &DispValue, const MCExpr *&DispExpr,
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MCInst *&PCRelBaseOut, MCInst *&FixedEntryLoadInst) const override {
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MemLocInstr = nullptr;
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BaseRegNum = 0;
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IndexRegNum = 0;
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DispValue = 0;
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DispExpr = nullptr;
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PCRelBaseOut = nullptr;
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FixedEntryLoadInst = nullptr;
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// Check for the following long tail call sequence:
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// 1: auipc xi, %pcrel_hi(sym)
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// jalr zero, %pcrel_lo(1b)(xi)
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if (Instruction.getOpcode() == RISCV::JALR && Begin != End) {
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MCInst &PrevInst = *std::prev(End);
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if (isRISCVCall(PrevInst, Instruction) &&
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Instruction.getOperand(0).getReg() == RISCV::X0)
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return IndirectBranchType::POSSIBLE_TAIL_CALL;
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}
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return IndirectBranchType::UNKNOWN;
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}
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bool convertJmpToTailCall(MCInst &Inst) override {
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if (isTailCall(Inst))
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return false;
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switch (Inst.getOpcode()) {
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default:
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llvm_unreachable("unsupported tail call opcode");
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case RISCV::JAL:
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case RISCV::JALR:
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case RISCV::C_J:
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case RISCV::C_JR:
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break;
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}
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setTailCall(Inst);
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return true;
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}
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void createReturn(MCInst &Inst) const override {
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// TODO "c.jr ra" when RVC is enabled
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Inst.setOpcode(RISCV::JALR);
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Inst.clear();
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Inst.addOperand(MCOperand::createReg(RISCV::X0));
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Inst.addOperand(MCOperand::createReg(RISCV::X1));
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Inst.addOperand(MCOperand::createImm(0));
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}
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void createUncondBranch(MCInst &Inst, const MCSymbol *TBB,
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MCContext *Ctx) const override {
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Inst.setOpcode(RISCV::JAL);
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Inst.clear();
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Inst.addOperand(MCOperand::createReg(RISCV::X0));
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Inst.addOperand(MCOperand::createExpr(MCSymbolRefExpr::create(TBB, *Ctx)));
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}
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StringRef getTrapFillValue() const override {
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return StringRef("\0\0\0\0", 4);
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}
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void createCall(unsigned Opcode, MCInst &Inst, const MCSymbol *Target,
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MCContext *Ctx) {
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Inst.setOpcode(Opcode);
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Inst.clear();
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Inst.addOperand(MCOperand::createExpr(MCSpecifierExpr::create(
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MCSymbolRefExpr::create(Target, *Ctx), ELF::R_RISCV_CALL_PLT, *Ctx)));
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}
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void createCall(MCInst &Inst, const MCSymbol *Target,
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MCContext *Ctx) override {
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return createCall(RISCV::PseudoCALL, Inst, Target, Ctx);
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}
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void createLongTailCall(InstructionListType &Seq, const MCSymbol *Target,
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MCContext *Ctx) override {
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createShortJmp(Seq, Target, Ctx, /*IsTailCall*/ true);
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}
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void createTailCall(MCInst &Inst, const MCSymbol *Target,
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MCContext *Ctx) override {
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return createCall(RISCV::PseudoTAIL, Inst, Target, Ctx);
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}
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bool analyzeBranch(InstructionIterator Begin, InstructionIterator End,
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const MCSymbol *&TBB, const MCSymbol *&FBB,
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MCInst *&CondBranch,
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MCInst *&UncondBranch) const override {
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auto I = End;
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while (I != Begin) {
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--I;
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// Ignore nops and CFIs
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if (isPseudo(*I) || isNoop(*I))
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continue;
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// Stop when we find the first non-terminator
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if (!isTerminator(*I) || isTailCall(*I) || !isBranch(*I))
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break;
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// Handle unconditional branches.
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if (isUnconditionalBranch(*I)) {
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// If any code was seen after this unconditional branch, we've seen
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// unreachable code. Ignore them.
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CondBranch = nullptr;
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UncondBranch = &*I;
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const MCSymbol *Sym = getTargetSymbol(*I);
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assert(Sym != nullptr &&
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"Couldn't extract BB symbol from jump operand");
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TBB = Sym;
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continue;
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}
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// Handle conditional branches and ignore indirect branches
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if (isIndirectBranch(*I))
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return false;
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if (CondBranch == nullptr) {
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const MCSymbol *TargetBB = getTargetSymbol(*I);
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if (TargetBB == nullptr) {
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// Unrecognized branch target
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return false;
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}
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FBB = TBB;
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TBB = TargetBB;
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CondBranch = &*I;
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continue;
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}
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llvm_unreachable("multiple conditional branches in one BB");
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}
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return true;
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}
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bool getSymbolRefOperandNum(const MCInst &Inst, unsigned &OpNum) const {
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switch (Inst.getOpcode()) {
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default:
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return false;
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case RISCV::C_J:
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OpNum = 0;
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return true;
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case RISCV::AUIPC:
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case RISCV::JAL:
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case RISCV::C_BEQZ:
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case RISCV::C_BNEZ:
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OpNum = 1;
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return true;
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case RISCV::BEQ:
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case RISCV::BGE:
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case RISCV::BGEU:
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case RISCV::BNE:
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case RISCV::BLT:
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case RISCV::BLTU:
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OpNum = 2;
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return true;
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}
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}
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const MCSymbol *getTargetSymbol(const MCExpr *Expr) const override {
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auto *RISCVExpr = dyn_cast<MCSpecifierExpr>(Expr);
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if (RISCVExpr && RISCVExpr->getSubExpr())
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return getTargetSymbol(RISCVExpr->getSubExpr());
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return MCPlusBuilder::getTargetSymbol(Expr);
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}
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const MCSymbol *getTargetSymbol(const MCInst &Inst,
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unsigned OpNum = 0) const override {
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if (!OpNum && !getSymbolRefOperandNum(Inst, OpNum))
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return nullptr;
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const MCOperand &Op = Inst.getOperand(OpNum);
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if (!Op.isExpr())
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return nullptr;
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return getTargetSymbol(Op.getExpr());
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}
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bool lowerTailCall(MCInst &Inst) override {
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removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall);
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if (getConditionalTailCall(Inst))
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unsetConditionalTailCall(Inst);
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return true;
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}
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uint64_t analyzePLTEntry(MCInst &Instruction, InstructionIterator Begin,
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InstructionIterator End,
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uint64_t BeginPC) const override {
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auto I = Begin;
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assert(I != End);
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auto &AUIPC = *I++;
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assert(AUIPC.getOpcode() == RISCV::AUIPC);
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assert(AUIPC.getOperand(0).getReg() == RISCV::X28);
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assert(I != End);
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auto &LD = *I++;
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assert(LD.getOpcode() == RISCV::LD);
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assert(LD.getOperand(0).getReg() == RISCV::X28);
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assert(LD.getOperand(1).getReg() == RISCV::X28);
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assert(I != End);
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auto &JALR = *I++;
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(void)JALR;
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assert(JALR.getOpcode() == RISCV::JALR);
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assert(JALR.getOperand(0).getReg() == RISCV::X6);
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assert(JALR.getOperand(1).getReg() == RISCV::X28);
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assert(I != End);
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auto &NOP = *I++;
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(void)NOP;
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assert(isNoop(NOP));
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assert(I == End);
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auto AUIPCOffset = AUIPC.getOperand(1).getImm() << 12;
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auto LDOffset = LD.getOperand(2).getImm();
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return BeginPC + AUIPCOffset + LDOffset;
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}
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bool replaceImmWithSymbolRef(MCInst &Inst, const MCSymbol *Symbol,
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int64_t Addend, MCContext *Ctx, int64_t &Value,
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uint32_t RelType) const override {
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unsigned ImmOpNo = -1U;
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for (unsigned Index = 0; Index < MCPlus::getNumPrimeOperands(Inst);
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++Index) {
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if (Inst.getOperand(Index).isImm()) {
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ImmOpNo = Index;
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break;
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}
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}
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if (ImmOpNo == -1U)
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return false;
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Value = Inst.getOperand(ImmOpNo).getImm();
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setOperandToSymbolRef(Inst, ImmOpNo, Symbol, Addend, Ctx, RelType);
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return true;
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}
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const MCExpr *getTargetExprFor(MCInst &Inst, const MCExpr *Expr,
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MCContext &Ctx,
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uint32_t RelType) const override {
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switch (RelType) {
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default:
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return Expr;
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case ELF::R_RISCV_GOT_HI20:
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case ELF::R_RISCV_TLS_GOT_HI20:
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case ELF::R_RISCV_TLS_GD_HI20:
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// The GOT is reused so no need to create GOT relocations
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case ELF::R_RISCV_PCREL_HI20:
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return MCSpecifierExpr::create(Expr, ELF::R_RISCV_PCREL_HI20, Ctx);
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case ELF::R_RISCV_PCREL_LO12_I:
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case ELF::R_RISCV_PCREL_LO12_S:
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return MCSpecifierExpr::create(Expr, RISCV::S_PCREL_LO, Ctx);
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case ELF::R_RISCV_HI20:
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return MCSpecifierExpr::create(Expr, ELF::R_RISCV_HI20, Ctx);
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case ELF::R_RISCV_LO12_I:
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case ELF::R_RISCV_LO12_S:
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return MCSpecifierExpr::create(Expr, RISCV::S_LO, Ctx);
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case ELF::R_RISCV_CALL:
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return MCSpecifierExpr::create(Expr, ELF::R_RISCV_CALL_PLT, Ctx);
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case ELF::R_RISCV_CALL_PLT:
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return MCSpecifierExpr::create(Expr, ELF::R_RISCV_CALL_PLT, Ctx);
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}
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}
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bool evaluateMemOperandTarget(const MCInst &Inst, uint64_t &Target,
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uint64_t Address,
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uint64_t Size) const override {
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return false;
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}
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bool isCallAuipc(const MCInst &Inst) const {
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if (Inst.getOpcode() != RISCV::AUIPC)
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return false;
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const auto &ImmOp = Inst.getOperand(1);
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if (!ImmOp.isExpr())
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return false;
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const auto *ImmExpr = ImmOp.getExpr();
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if (!isa<MCSpecifierExpr>(ImmExpr))
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return false;
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switch (cast<MCSpecifierExpr>(ImmExpr)->getSpecifier()) {
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default:
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return false;
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case ELF::R_RISCV_CALL_PLT:
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return true;
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}
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}
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bool isRISCVCall(const MCInst &First, const MCInst &Second) const override {
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if (!isCallAuipc(First))
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return false;
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assert(Second.getOpcode() == RISCV::JALR);
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return true;
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}
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uint16_t getMinFunctionAlignment() const override {
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if (STI->hasFeature(RISCV::FeatureStdExtC) ||
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STI->hasFeature(RISCV::FeatureStdExtZca))
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return 2;
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return 4;
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}
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void createStackPointerIncrement(
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MCInst &Inst, int imm,
|
|
bool NoFlagsClobber = false /*unused for RISCV*/) const override {
|
|
Inst = MCInstBuilder(RISCV::ADDI)
|
|
.addReg(RISCV::X2)
|
|
.addReg(RISCV::X2)
|
|
.addImm(-imm);
|
|
}
|
|
|
|
void createStackPointerDecrement(
|
|
MCInst &Inst, int imm,
|
|
bool NoFlagsClobber = false /*unused for RISCV*/) const override {
|
|
Inst = MCInstBuilder(RISCV::ADDI)
|
|
.addReg(RISCV::X2)
|
|
.addReg(RISCV::X2)
|
|
.addImm(imm);
|
|
}
|
|
|
|
void loadReg(MCInst &Inst, MCPhysReg To, MCPhysReg From,
|
|
int64_t offset) const {
|
|
Inst = MCInstBuilder(RISCV::LD).addReg(To).addReg(From).addImm(offset);
|
|
}
|
|
|
|
void storeReg(MCInst &Inst, MCPhysReg From, MCPhysReg To,
|
|
int64_t offset) const {
|
|
Inst = MCInstBuilder(RISCV::SD).addReg(From).addReg(To).addImm(offset);
|
|
}
|
|
|
|
void spillRegs(InstructionListType &Insts,
|
|
const SmallVector<unsigned> &Regs) const {
|
|
Insts.emplace_back();
|
|
createStackPointerIncrement(Insts.back(), Regs.size() * 8);
|
|
|
|
int64_t Offset = 0;
|
|
for (auto Reg : Regs) {
|
|
Insts.emplace_back();
|
|
storeReg(Insts.back(), Reg, RISCV::X2, Offset);
|
|
Offset += 8;
|
|
}
|
|
}
|
|
|
|
void reloadRegs(InstructionListType &Insts,
|
|
const SmallVector<unsigned> &Regs) const {
|
|
int64_t Offset = 0;
|
|
for (auto Reg : Regs) {
|
|
Insts.emplace_back();
|
|
loadReg(Insts.back(), Reg, RISCV::X2, Offset);
|
|
Offset += 8;
|
|
}
|
|
|
|
Insts.emplace_back();
|
|
createStackPointerDecrement(Insts.back(), Regs.size() * 8);
|
|
}
|
|
|
|
void atomicAdd(MCInst &Inst, MCPhysReg RegAtomic, MCPhysReg RegTo,
|
|
MCPhysReg RegCnt) const {
|
|
Inst = MCInstBuilder(RISCV::AMOADD_D)
|
|
.addReg(RegAtomic)
|
|
.addReg(RegTo)
|
|
.addReg(RegCnt);
|
|
}
|
|
|
|
InstructionListType createRegCmpJE(MCPhysReg RegNo, MCPhysReg RegTmp,
|
|
const MCSymbol *Target,
|
|
MCContext *Ctx) const {
|
|
InstructionListType Insts;
|
|
Insts.emplace_back(
|
|
MCInstBuilder(RISCV::SUB).addReg(RegTmp).addReg(RegNo).addReg(RegNo));
|
|
Insts.emplace_back(MCInstBuilder(RISCV::BEQ)
|
|
.addReg(RegNo)
|
|
.addReg(RegTmp)
|
|
.addExpr(MCSymbolRefExpr::create(Target, *Ctx)));
|
|
return Insts;
|
|
}
|
|
|
|
void createTrap(MCInst &Inst) const override {
|
|
Inst.clear();
|
|
Inst.setOpcode(RISCV::EBREAK);
|
|
}
|
|
|
|
void createShortJmp(InstructionListType &Seq, const MCSymbol *Target,
|
|
MCContext *Ctx, bool IsTailCall) override {
|
|
// The sequence of instructions we create here is the following:
|
|
// auipc a5, hi20(Target)
|
|
// addi a5, a5, low12(Target)
|
|
// jr x5 => jalr x0, x5, 0
|
|
MCPhysReg Reg = RISCV::X5;
|
|
InstructionListType Insts = materializeAddress(Target, Ctx, Reg);
|
|
Insts.emplace_back();
|
|
MCInst &Inst = Insts.back();
|
|
Inst.clear();
|
|
Inst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Reg).addImm(0);
|
|
if (IsTailCall)
|
|
setTailCall(Inst);
|
|
Seq.swap(Insts);
|
|
}
|
|
|
|
InstructionListType createGetter(MCContext *Ctx, const char *name) const {
|
|
InstructionListType Insts(4);
|
|
MCSymbol *Locs = Ctx->getOrCreateSymbol(name);
|
|
InstructionListType Addr = materializeAddress(Locs, Ctx, RISCV::X10);
|
|
std::copy(Addr.begin(), Addr.end(), Insts.begin());
|
|
loadReg(Insts[2], RISCV::X10, RISCV::X10, 0);
|
|
createReturn(Insts[3]);
|
|
return Insts;
|
|
}
|
|
|
|
InstructionListType createIncMemory(MCPhysReg RegTo, MCPhysReg RegCnt,
|
|
MCPhysReg RegAtomic) const {
|
|
InstructionListType Insts;
|
|
Insts.emplace_back();
|
|
Insts.back() =
|
|
MCInstBuilder(RISCV::ADDI).addReg(RegCnt).addReg(RegAtomic).addImm(1);
|
|
Insts.emplace_back();
|
|
atomicAdd(Insts.back(), RegAtomic, RegTo, RegCnt);
|
|
return Insts;
|
|
}
|
|
|
|
InstructionListType materializeAddress(const MCSymbol *Target, MCContext *Ctx,
|
|
MCPhysReg RegName,
|
|
int64_t Addend = 0) const override {
|
|
// Get the symbol address by auipc + addi
|
|
InstructionListType Insts(2);
|
|
MCSymbol *AuipcLabel = Ctx->createNamedTempSymbol("pcrel_hi");
|
|
Insts[0] = MCInstBuilder(RISCV::AUIPC).addReg(RegName).addImm(0);
|
|
setOperandToSymbolRef(Insts[0], /* OpNum */ 1, Target, Addend, Ctx,
|
|
ELF::R_RISCV_PCREL_HI20);
|
|
setInstLabel(Insts[0], AuipcLabel);
|
|
|
|
Insts[1] =
|
|
MCInstBuilder(RISCV::ADDI).addReg(RegName).addReg(RegName).addImm(0);
|
|
setOperandToSymbolRef(Insts[1], /* OpNum */ 2, AuipcLabel, Addend, Ctx,
|
|
ELF::R_RISCV_PCREL_LO12_I);
|
|
return Insts;
|
|
}
|
|
|
|
InstructionListType
|
|
createInstrIncMemory(const MCSymbol *Target, MCContext *Ctx, bool IsLeaf,
|
|
unsigned CodePointerSize) const override {
|
|
// We need 2 scratch registers: one for the target address (x10), and one
|
|
// for the increment value (x11).
|
|
// addi sp, sp, -16
|
|
// sd x10, 0(sp)
|
|
// sd x11, 8(sp)
|
|
// la x10, target # 1: auipc x10, %pcrel_hi(target)
|
|
// # addi x10, x10, %pcrel_lo(1b)
|
|
// li x11, 1 # addi x11, zero, 1
|
|
// amoadd.d zero, x10, x11
|
|
// ld x10, 0(sp)
|
|
// ld x11, 8(sp)
|
|
// addi sp, sp, 16
|
|
|
|
InstructionListType Insts;
|
|
spillRegs(Insts, {RISCV::X10, RISCV::X11});
|
|
InstructionListType Addr = materializeAddress(Target, Ctx, RISCV::X10);
|
|
Insts.insert(Insts.end(), Addr.begin(), Addr.end());
|
|
InstructionListType IncInsts =
|
|
createIncMemory(RISCV::X10, RISCV::X11, RISCV::X0);
|
|
Insts.insert(Insts.end(), IncInsts.begin(), IncInsts.end());
|
|
reloadRegs(Insts, {RISCV::X10, RISCV::X11});
|
|
return Insts;
|
|
}
|
|
|
|
void createDirectCall(MCInst &Inst, const MCSymbol *Target, MCContext *Ctx,
|
|
bool IsTailCall) override {
|
|
Inst.setOpcode(RISCV::JAL);
|
|
Inst.clear();
|
|
if (IsTailCall) {
|
|
Inst.addOperand(MCOperand::createReg(RISCV::X0));
|
|
Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
|
|
Inst, MCSymbolRefExpr::create(Target, *Ctx), *Ctx, 0)));
|
|
convertJmpToTailCall(Inst);
|
|
} else {
|
|
Inst.addOperand(MCOperand::createReg(RISCV::X1));
|
|
Inst.addOperand(MCOperand::createExpr(getTargetExprFor(
|
|
Inst, MCSymbolRefExpr::create(Target, *Ctx), *Ctx, 0)));
|
|
}
|
|
}
|
|
|
|
void createIndirectCallInst(MCInst &Inst, bool IsTailCall, MCPhysReg Reg,
|
|
int64_t Disp) const {
|
|
Inst.clear();
|
|
Inst.setOpcode(RISCV::JALR);
|
|
Inst.clear();
|
|
if (IsTailCall) {
|
|
Inst.addOperand(MCOperand::createReg(RISCV::X0));
|
|
Inst.addOperand(MCOperand::createReg(Reg));
|
|
Inst.addOperand(MCOperand::createImm(Disp));
|
|
} else {
|
|
Inst.addOperand(MCOperand::createReg(RISCV::X1));
|
|
Inst.addOperand(MCOperand::createReg(Reg));
|
|
Inst.addOperand(MCOperand::createImm(Disp));
|
|
}
|
|
}
|
|
|
|
InstructionListType
|
|
createInstrumentedIndCallHandlerEntryBB(const MCSymbol *InstrTrampoline,
|
|
const MCSymbol *IndCallHandler,
|
|
MCContext *Ctx) override {
|
|
// Code sequence used to check whether InstrTampoline was initialized
|
|
// and call it if so, returns via IndCallHandler
|
|
// sp -16(sp)
|
|
// sd x10, 0(sp)
|
|
// sd x11, 0(sp)
|
|
// la x10, InstrTrampoline -> auipc + addi
|
|
// ld x10, [x10]
|
|
// beq x10, x11, IndCallHandler
|
|
// sp -16(sp)
|
|
// sd x1, 0(sp)
|
|
// jalr x1,x10,0
|
|
// ld x1, [sp], #16
|
|
// sp 16(sp)
|
|
// jal x0, IndCallHandler
|
|
|
|
InstructionListType Insts;
|
|
spillRegs(Insts, {RISCV::X10, RISCV::X11});
|
|
InstructionListType Addr =
|
|
materializeAddress(InstrTrampoline, Ctx, RISCV::X10);
|
|
Insts.insert(Insts.end(), Addr.begin(), Addr.end());
|
|
Insts.emplace_back();
|
|
loadReg(Insts.back(), RISCV::X10, RISCV::X10, 0);
|
|
InstructionListType cmpJmp =
|
|
createRegCmpJE(RISCV::X10, RISCV::X11, IndCallHandler, Ctx);
|
|
Insts.insert(Insts.end(), cmpJmp.begin(), cmpJmp.end());
|
|
Insts.emplace_back();
|
|
createStackPointerIncrement(Insts.back(), 16);
|
|
Insts.emplace_back();
|
|
storeReg(Insts.back(), RISCV::X1, RISCV::X2, 0);
|
|
Insts.emplace_back();
|
|
createIndirectCallInst(Insts.back(), /*IsTailCall*/ false, RISCV::X10, 0);
|
|
Insts.emplace_back();
|
|
loadReg(Insts.back(), RISCV::X1, RISCV::X2, 0);
|
|
Insts.emplace_back();
|
|
createStackPointerDecrement(Insts.back(), 16);
|
|
Insts.emplace_back();
|
|
createDirectCall(Insts.back(), IndCallHandler, Ctx, /*IsTailCall*/ true);
|
|
return Insts;
|
|
}
|
|
|
|
InstructionListType createInstrumentedIndCallHandlerExitBB() const override {
|
|
InstructionListType Insts;
|
|
reloadRegs(Insts, {RISCV::X10, RISCV::X11});
|
|
Insts.emplace_back();
|
|
loadReg(Insts.back(), RISCV::X5, RISCV::X2, 0);
|
|
Insts.emplace_back();
|
|
createStackPointerDecrement(Insts.back(), 16);
|
|
reloadRegs(Insts, {RISCV::X10, RISCV::X11});
|
|
Insts.emplace_back();
|
|
createIndirectCallInst(Insts.back(), /*IsTailCall*/ true, RISCV::X5, 0);
|
|
return Insts;
|
|
}
|
|
|
|
InstructionListType
|
|
createInstrumentedIndTailCallHandlerExitBB() const override {
|
|
return createInstrumentedIndCallHandlerExitBB();
|
|
}
|
|
|
|
std::vector<MCInst> createSymbolTrampoline(const MCSymbol *TgtSym,
|
|
MCContext *Ctx) override {
|
|
std::vector<MCInst> Insts;
|
|
createShortJmp(Insts, TgtSym, Ctx, /*IsTailCall*/ true);
|
|
return Insts;
|
|
}
|
|
|
|
InstructionListType createNumCountersGetter(MCContext *Ctx) const override {
|
|
return createGetter(Ctx, "__bolt_num_counters");
|
|
}
|
|
|
|
InstructionListType
|
|
createInstrLocationsGetter(MCContext *Ctx) const override {
|
|
return createGetter(Ctx, "__bolt_instr_locations");
|
|
}
|
|
|
|
InstructionListType createInstrTablesGetter(MCContext *Ctx) const override {
|
|
return createGetter(Ctx, "__bolt_instr_tables");
|
|
}
|
|
|
|
InstructionListType createInstrNumFuncsGetter(MCContext *Ctx) const override {
|
|
return createGetter(Ctx, "__bolt_instr_num_funcs");
|
|
}
|
|
|
|
void convertIndirectCallToLoad(MCInst &Inst, MCPhysReg Reg) override {
|
|
bool IsTailCall = isTailCall(Inst);
|
|
if (IsTailCall)
|
|
removeAnnotation(Inst, MCPlus::MCAnnotation::kTailCall);
|
|
Inst.setOpcode(RISCV::ADD);
|
|
Inst.insert(Inst.begin(), MCOperand::createReg(Reg));
|
|
Inst.insert(Inst.begin() + 1, MCOperand::createReg(RISCV::X0));
|
|
}
|
|
|
|
InstructionListType createLoadImmediate(const MCPhysReg Dest,
|
|
uint64_t Imm) const override {
|
|
InstructionListType Insts;
|
|
// get IMM higher 32bit
|
|
Insts.emplace_back(
|
|
MCInstBuilder(RISCV::LUI).addReg(Dest).addImm((Imm >> 44) & 0xFFFFF));
|
|
Insts.emplace_back(MCInstBuilder(RISCV::LUI)
|
|
.addReg(RISCV::X5)
|
|
.addImm((Imm >> 32) & 0xFFF));
|
|
Insts.emplace_back(MCInstBuilder(RISCV::SRLI)
|
|
.addReg(RISCV::X5)
|
|
.addReg(RISCV::X5)
|
|
.addImm(12));
|
|
Insts.emplace_back(
|
|
MCInstBuilder(RISCV::OR).addReg(Dest).addReg(Dest).addReg(RISCV::X5));
|
|
Insts.emplace_back(
|
|
MCInstBuilder(RISCV::SLLI).addReg(Dest).addReg(Dest).addImm(32));
|
|
|
|
// get IMM lower 32bit
|
|
Insts.emplace_back(MCInstBuilder(RISCV::LUI)
|
|
.addReg(RISCV::X5)
|
|
.addImm((Imm >> 12) & 0xFFFFF));
|
|
Insts.emplace_back(
|
|
MCInstBuilder(RISCV::LUI).addReg(RISCV::X6).addImm((Imm)&0xFFF));
|
|
Insts.emplace_back(MCInstBuilder(RISCV::SRLI)
|
|
.addReg(RISCV::X6)
|
|
.addReg(RISCV::X6)
|
|
.addImm(12));
|
|
Insts.emplace_back(
|
|
MCInstBuilder(RISCV::OR).addReg(RISCV::X5).addReg(RISCV::X5).addReg(
|
|
RISCV::X6));
|
|
|
|
// get 64bit IMM
|
|
Insts.emplace_back(
|
|
MCInstBuilder(RISCV::OR).addReg(Dest).addReg(Dest).addReg(RISCV::X5));
|
|
return Insts;
|
|
}
|
|
|
|
InstructionListType createInstrumentedIndirectCall(MCInst &&CallInst,
|
|
MCSymbol *HandlerFuncAddr,
|
|
int CallSiteID,
|
|
MCContext *Ctx) override {
|
|
// Code sequence used to enter indirect call instrumentation helper:
|
|
// addi sp, sp, -0x10
|
|
// sd a0, 0x0(sp)
|
|
// sd a1, 0x8(sp)
|
|
// mov target x0 convertIndirectCallToLoad -> add a0, zero, target
|
|
// mov x1 CallSiteID createLoadImmediate
|
|
// addi sp, sp, -0x10
|
|
// sd a0, 0x0(sp)
|
|
// sd a1, 0x8(sp)
|
|
// la x0 *HandlerFuncAddr -> auipc + addi
|
|
// jalr x0
|
|
|
|
InstructionListType Insts;
|
|
spillRegs(Insts, {RISCV::X10, RISCV::X11});
|
|
Insts.emplace_back(CallInst);
|
|
convertIndirectCallToLoad(Insts.back(), RISCV::X10);
|
|
InstructionListType LoadImm = createLoadImmediate(RISCV::X11, CallSiteID);
|
|
Insts.insert(Insts.end(), LoadImm.begin(), LoadImm.end());
|
|
spillRegs(Insts, {RISCV::X10, RISCV::X11});
|
|
InstructionListType Addr =
|
|
materializeAddress(HandlerFuncAddr, Ctx, RISCV::X5);
|
|
Insts.insert(Insts.end(), Addr.begin(), Addr.end());
|
|
Insts.emplace_back();
|
|
createIndirectCallInst(Insts.back(), isTailCall(CallInst), RISCV::X5, 0);
|
|
|
|
// // Carry over metadata including tail call marker if present.
|
|
stripAnnotations(Insts.back());
|
|
moveAnnotations(std::move(CallInst), Insts.back());
|
|
|
|
return Insts;
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
namespace llvm {
|
|
namespace bolt {
|
|
|
|
MCPlusBuilder *createRISCVMCPlusBuilder(const MCInstrAnalysis *Analysis,
|
|
const MCInstrInfo *Info,
|
|
const MCRegisterInfo *RegInfo,
|
|
const MCSubtargetInfo *STI) {
|
|
return new RISCVMCPlusBuilder(Analysis, Info, RegInfo, STI);
|
|
}
|
|
|
|
} // namespace bolt
|
|
} // namespace llvm
|