92a966bd8f
-mcpu is used to determine the ISA string if an explicit -march is not present on the command line. If there is a -march present it always has priority over -mcpu regardless of where it appears in the command line. This can cause issues if -march appears in a Makefile and a user wants to override it with an -mcpu on the command line. The user would need to provide a potentially long ISA string to -march that matches the -mcpu in order to override the MakeFile. This issue can also be seen on Compiler Explorer where the rv64gc toolchain is passed -march=rv64gc before any user command line options are added. If you pass -mcpu=spacemit-x60, vectors will not be enabled due to the hidden -march. This patch adds a new option for -march, "unset" that makes the -march ignored for purposes of prioritizing over -mcpu. Now a user can write -march=unset -mcpu=<cpu_name>. This is also implemented by gcc for ARM32. An alternative would be to allow -march to take a cpu name, but that requires "-march=<cpu_name> -mcpu=<cpu_name>" or "-march=<cpu_name> -mtune=<cpu_name>" to ensure the tune cpu also gets updated. IMHO, needing to repeat the CPU name twice isn't friendly and invites mistakes. gcc has implemented this as well.
370 lines
13 KiB
C++
370 lines
13 KiB
C++
//===--- RISCV.cpp - RISC-V Helpers for Tools -------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "../Clang.h"
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#include "clang/Driver/CommonArgs.h"
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#include "clang/Driver/Driver.h"
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#include "clang/Driver/Options.h"
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#include "llvm/Option/ArgList.h"
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#include "llvm/Support/Error.h"
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#include "llvm/TargetParser/Host.h"
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#include "llvm/TargetParser/RISCVISAInfo.h"
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#include "llvm/TargetParser/RISCVTargetParser.h"
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using namespace clang::driver;
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using namespace clang::driver::tools;
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using namespace clang;
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using namespace llvm::opt;
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// Returns false if an error is diagnosed.
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static bool getArchFeatures(const Driver &D, StringRef Arch,
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std::vector<StringRef> &Features,
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const ArgList &Args) {
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bool EnableExperimentalExtensions =
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Args.hasArg(options::OPT_menable_experimental_extensions);
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auto ISAInfo =
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llvm::RISCVISAInfo::parseArchString(Arch, EnableExperimentalExtensions);
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if (!ISAInfo) {
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handleAllErrors(ISAInfo.takeError(), [&](llvm::StringError &ErrMsg) {
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D.Diag(diag::err_drv_invalid_riscv_arch_name)
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<< Arch << ErrMsg.getMessage();
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});
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return false;
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}
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for (const std::string &Str : (*ISAInfo)->toFeatures(/*AddAllExtension=*/true,
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/*IgnoreUnknown=*/false))
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Features.push_back(Args.MakeArgString(Str));
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if (EnableExperimentalExtensions)
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Features.push_back(Args.MakeArgString("+experimental"));
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return true;
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}
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// Get features except standard extension feature
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static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
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const llvm::Triple &Triple,
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StringRef Mcpu,
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std::vector<StringRef> &Features) {
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bool Is64Bit = Triple.isRISCV64();
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if (!llvm::RISCV::parseCPU(Mcpu, Is64Bit)) {
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// Try inverting Is64Bit in case the CPU is valid, but for the wrong target.
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if (llvm::RISCV::parseCPU(Mcpu, !Is64Bit))
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D.Diag(clang::diag::err_drv_invalid_riscv_cpu_name_for_target)
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<< Mcpu << Is64Bit;
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else
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D.Diag(clang::diag::err_drv_unsupported_option_argument)
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<< A->getSpelling() << Mcpu;
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}
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}
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void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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const ArgList &Args,
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std::vector<StringRef> &Features) {
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std::string MArch = getRISCVArch(Args, Triple);
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if (!getArchFeatures(D, MArch, Features, Args))
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return;
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bool CPUFastScalarUnaligned = false;
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bool CPUFastVectorUnaligned = false;
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// If users give march and mcpu, get std extension feature from MArch
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// and other features (ex. mirco architecture feature) from mcpu
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if (Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
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StringRef CPU = A->getValue();
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if (CPU == "native")
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CPU = llvm::sys::getHostCPUName();
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getRISCFeaturesFromMcpu(D, A, Triple, CPU, Features);
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if (llvm::RISCV::hasFastScalarUnalignedAccess(CPU))
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CPUFastScalarUnaligned = true;
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if (llvm::RISCV::hasFastVectorUnalignedAccess(CPU))
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CPUFastVectorUnaligned = true;
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}
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// Handle features corresponding to "-ffixed-X" options
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#define RESERVE_REG(REG) \
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if (Args.hasArg(options::OPT_ffixed_##REG)) \
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Features.push_back("+reserve-" #REG);
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RESERVE_REG(x1)
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RESERVE_REG(x2)
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RESERVE_REG(x3)
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RESERVE_REG(x4)
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RESERVE_REG(x5)
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RESERVE_REG(x6)
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RESERVE_REG(x7)
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RESERVE_REG(x8)
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RESERVE_REG(x9)
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RESERVE_REG(x10)
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RESERVE_REG(x11)
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RESERVE_REG(x12)
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RESERVE_REG(x13)
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RESERVE_REG(x14)
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RESERVE_REG(x15)
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RESERVE_REG(x16)
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RESERVE_REG(x17)
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RESERVE_REG(x18)
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RESERVE_REG(x19)
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RESERVE_REG(x20)
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RESERVE_REG(x21)
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RESERVE_REG(x22)
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RESERVE_REG(x23)
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RESERVE_REG(x24)
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RESERVE_REG(x25)
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RESERVE_REG(x26)
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RESERVE_REG(x27)
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RESERVE_REG(x28)
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RESERVE_REG(x29)
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RESERVE_REG(x30)
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RESERVE_REG(x31)
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#undef RESERVE_REG
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// -mrelax is default, unless -mno-relax is specified.
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if (Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true)) {
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Features.push_back("+relax");
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// -gsplit-dwarf -mrelax requires DW_AT_high_pc/DW_AT_ranges/... indexing
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// into .debug_addr, which is currently not implemented.
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Arg *A;
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if (getDebugFissionKind(D, Args, A) != DwarfFissionKind::None)
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D.Diag(clang::diag::err_drv_riscv_unsupported_with_linker_relaxation)
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<< A->getAsString(Args);
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} else {
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Features.push_back("-relax");
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}
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// If -mstrict-align, -mno-strict-align, -mscalar-strict-align, or
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// -mno-scalar-strict-align is passed, use it. Otherwise, the
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// unaligned-scalar-mem is enabled if the CPU supports it or the target is
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// Android.
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if (const Arg *A = Args.getLastArg(
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options::OPT_mno_strict_align, options::OPT_mscalar_strict_align,
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options::OPT_mstrict_align, options::OPT_mno_scalar_strict_align)) {
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if (A->getOption().matches(options::OPT_mno_strict_align) ||
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A->getOption().matches(options::OPT_mno_scalar_strict_align)) {
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Features.push_back("+unaligned-scalar-mem");
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} else {
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Features.push_back("-unaligned-scalar-mem");
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}
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} else if (CPUFastScalarUnaligned || Triple.isAndroid()) {
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Features.push_back("+unaligned-scalar-mem");
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}
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// If -mstrict-align, -mno-strict-align, -mvector-strict-align, or
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// -mno-vector-strict-align is passed, use it. Otherwise, the
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// unaligned-vector-mem is enabled if the CPU supports it or the target is
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// Android.
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if (const Arg *A = Args.getLastArg(
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options::OPT_mno_strict_align, options::OPT_mvector_strict_align,
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options::OPT_mstrict_align, options::OPT_mno_vector_strict_align)) {
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if (A->getOption().matches(options::OPT_mno_strict_align) ||
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A->getOption().matches(options::OPT_mno_vector_strict_align)) {
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Features.push_back("+unaligned-vector-mem");
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} else {
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Features.push_back("-unaligned-vector-mem");
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}
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} else if (CPUFastVectorUnaligned || Triple.isAndroid()) {
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Features.push_back("+unaligned-vector-mem");
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}
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// Now add any that the user explicitly requested on the command line,
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// which may override the defaults.
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handleTargetFeaturesGroup(D, Triple, Args, Features,
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options::OPT_m_riscv_Features_Group);
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}
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StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
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assert(Triple.isRISCV() && "Unexpected triple");
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// GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
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// configured using `--with-abi=`, then the logic for the default choice is
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// defined in config.gcc. This function is based on the logic in GCC 9.2.0.
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//
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// The logic used in GCC 9.2.0 is the following, in order:
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// 1. Explicit choices using `--with-abi=`
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// 2. A default based on `--with-arch=`, if provided
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// 3. A default based on the target triple's arch
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//
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// The logic in config.gcc is a little circular but it is not inconsistent.
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//
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// Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
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// and `-mabi=` respectively instead.
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//
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// In order to make chosing logic more clear, Clang uses the following logic,
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// in order:
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// 1. Explicit choices using `-mabi=`
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// 2. A default based on the architecture as determined by getRISCVArch
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// 3. Choose a default based on the triple
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// 1. If `-mabi=` is specified, use it.
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if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
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return A->getValue();
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// 2. Choose a default based on the target architecture.
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//
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// rv32g | rv32*d -> ilp32d
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// rv32e -> ilp32e
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// rv32* -> ilp32
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// rv64g | rv64*d -> lp64d
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// rv64e -> lp64e
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// rv64* -> lp64
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std::string Arch = getRISCVArch(Args, Triple);
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auto ParseResult = llvm::RISCVISAInfo::parseArchString(
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Arch, /* EnableExperimentalExtension */ true);
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// Ignore parsing error, just go 3rd step.
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if (!llvm::errorToBool(ParseResult.takeError()))
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return (*ParseResult)->computeDefaultABI();
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// 3. Choose a default based on the triple
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//
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// We deviate from GCC's defaults here:
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// - On `riscv{XLEN}-unknown-elf` we use the integer calling convention only.
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// - On all other OSs we use the double floating point calling convention.
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if (Triple.isRISCV32()) {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "ilp32";
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else
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return "ilp32d";
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} else {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "lp64";
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else
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return "lp64d";
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}
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}
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std::string riscv::getRISCVArch(const llvm::opt::ArgList &Args,
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const llvm::Triple &Triple) {
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assert(Triple.isRISCV() && "Unexpected triple");
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// GCC's logic around choosing a default `-march=` is complex. If GCC is not
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// configured using `--with-arch=`, then the logic for the default choice is
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// defined in config.gcc. This function is based on the logic in GCC 9.2.0. We
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// deviate from GCC's default on additional `-mcpu` option (GCC does not
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// support `-mcpu`) and baremetal targets (UnknownOS) where neither `-march`
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// nor `-mabi` is specified.
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//
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// The logic used in GCC 9.2.0 is the following, in order:
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// 1. Explicit choices using `--with-arch=`
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// 2. A default based on `--with-abi=`, if provided
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// 3. A default based on the target triple's arch
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//
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// The logic in config.gcc is a little circular but it is not inconsistent.
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//
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// Clang does not have `--with-arch=` or `--with-abi=`, so we use `-march=`
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// and `-mabi=` respectively instead.
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//
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// Clang uses the following logic, in order:
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// 1. Explicit choices using `-march=`
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// 2. Based on `-mcpu` if the target CPU has a default ISA string
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// 3. A default based on `-mabi`, if provided
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// 4. A default based on the target triple's arch
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//
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// Clang does not yet support MULTILIB_REUSE, so we use `rv{XLEN}imafdc`
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// instead of `rv{XLEN}gc` though they are (currently) equivalent.
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// 1. If `-march=` is specified, use it unless the value is "unset".
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if (const Arg *A = Args.getLastArg(options::OPT_march_EQ)) {
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StringRef MArch = A->getValue();
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if (MArch != "unset")
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return MArch.str();
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}
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// 2. Get march (isa string) based on `-mcpu=`
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if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ)) {
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StringRef CPU = A->getValue();
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if (CPU == "native") {
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CPU = llvm::sys::getHostCPUName();
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// If the target cpu is unrecognized, use target features.
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if (CPU.starts_with("generic")) {
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auto FeatureMap = llvm::sys::getHostCPUFeatures();
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// hwprobe may be unavailable on older Linux versions.
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if (!FeatureMap.empty()) {
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std::vector<std::string> Features;
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for (auto &F : FeatureMap)
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Features.push_back(((F.second ? "+" : "-") + F.first()).str());
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auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
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Triple.isRISCV32() ? 32 : 64, Features);
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if (ParseResult)
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return (*ParseResult)->toString();
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}
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}
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}
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StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
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// Bypass if target cpu's default march is empty.
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if (!MArch.empty())
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return MArch.str();
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}
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// 3. Choose a default based on `-mabi=`
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//
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// ilp32e -> rv32e
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// lp64e -> rv64e
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// ilp32 | ilp32f | ilp32d -> rv32imafdc
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// lp64 | lp64f | lp64d -> rv64imafdc
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if (const Arg *A = Args.getLastArg(options::OPT_mabi_EQ)) {
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StringRef MABI = A->getValue();
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if (MABI.equals_insensitive("ilp32e"))
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return "rv32e";
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if (MABI.equals_insensitive("lp64e"))
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return "rv64e";
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if (MABI.starts_with_insensitive("ilp32"))
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return "rv32imafdc";
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if (MABI.starts_with_insensitive("lp64")) {
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if (Triple.isAndroid())
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return "rv64imafdcv_zba_zbb_zbs";
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if (Triple.isOSFuchsia())
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return "rva22u64_v";
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return "rv64imafdc";
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}
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}
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// 4. Choose a default based on the triple
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//
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// We deviate from GCC's defaults here:
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// - On `riscv{XLEN}-unknown-elf` we default to `rv{XLEN}imac`
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// - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
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if (Triple.isRISCV32()) {
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "rv32imac";
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return "rv32imafdc";
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}
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if (Triple.getOS() == llvm::Triple::UnknownOS)
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return "rv64imac";
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if (Triple.isAndroid())
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return "rv64imafdcv_zba_zbb_zbs";
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if (Triple.isOSFuchsia())
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return "rva22u64_v";
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return "rv64imafdc";
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}
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std::string riscv::getRISCVTargetCPU(const llvm::opt::ArgList &Args,
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const llvm::Triple &Triple) {
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std::string CPU;
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// If we have -mcpu, use that.
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if (const Arg *A = Args.getLastArg(options::OPT_mcpu_EQ))
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CPU = A->getValue();
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// Handle CPU name is 'native'.
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if (CPU == "native")
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CPU = llvm::sys::getHostCPUName();
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if (!CPU.empty())
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return CPU;
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return Triple.isRISCV64() ? "generic-rv64" : "generic-rv32";
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}
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