577ee97d4e
This PR fixes the access to bitfields inside a union.
Previously, we were using a `getMemberOp` to access the field, but
because it is a union, `getMemberOp` would always use index `0`.
For example, given:
```c
typedef union {
int x;
int y : 4;
int z : 8;
} demo;
```
```mlir
!rec_demo = !cir.record<union "demo" {!s32i, !u8i, !u8i}>
```
In the case of:
```c
d.y = 2;
```
It would generate:
```mlir
cir.get_member %0[0] {name = "y"} : !cir.ptr<!rec_demo> -> !cir.ptr<!s32i>
```
with a return type of `!s32i`, when it should be `!u8i`.
the get_member verifier would detect that the return type does not match
the `y` member.
To fix this, we now use `bitcast` to get the start of the union.
72 lines
2.8 KiB
C
72 lines
2.8 KiB
C
// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-cir %s -o %t.cir
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// RUN: FileCheck --input-file=%t.cir %s --check-prefix=CIR
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -fclangir -emit-llvm %s -o %t-cir.ll
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// RUN: FileCheck --input-file=%t-cir.ll %s --check-prefix=LLVM
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// RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm %s -o %t.ll
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// RUN: FileCheck --input-file=%t.ll %s --check-prefix=OGCG
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typedef union {
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int x;
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int y : 4;
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int z : 8;
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} demo;
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// CIR: !rec_demo = !cir.record<union "demo" {!s32i, !u8i, !u8i}>
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// LLVM: %union.demo = type { i32 }
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// OGCG: %union.demo = type { i32 }
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typedef union {
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int x;
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int y : 3;
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int : 0;
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int z : 2;
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} zero_bit;
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// CIR: !rec_zero_bit = !cir.record<union "zero_bit" {!s32i, !u8i, !u8i}>
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// LLVM: %union.zero_bit = type { i32 }
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// OGCG: %union.zero_bit = type { i32 }
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demo d;
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zero_bit z;
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void f() {
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demo d;
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d.x = 1;
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d.y = 2;
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d.z = 0;
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}
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// CIR: #bfi_y = #cir.bitfield_info<name = "y", storage_type = !u8i, size = 4, offset = 0, is_signed = true>
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// CIR: #bfi_z = #cir.bitfield_info<name = "z", storage_type = !u8i, size = 8, offset = 0, is_signed = true>
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// CIR: cir.func no_proto dso_local @f
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// CIR: [[ALLOC:%.*]] = cir.alloca !rec_demo, !cir.ptr<!rec_demo>, ["d"] {alignment = 4 : i64}
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// CIR: [[ONE:%.*]] = cir.const #cir.int<1> : !s32i
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// CIR: [[X:%.*]] = cir.get_member [[ALLOC]][0] {name = "x"} : !cir.ptr<!rec_demo> -> !cir.ptr<!s32i>
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// CIR: cir.store align(4) [[ONE]], [[X]] : !s32i, !cir.ptr<!s32i>
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// CIR: [[TWO:%.*]] = cir.const #cir.int<2> : !s32i
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// CIR: [[Y:%.*]] = cir.get_member [[ALLOC]][1] {name = "y"} : !cir.ptr<!rec_demo> -> !cir.ptr<!u8i>
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// CIR: [[SET:%.*]] = cir.set_bitfield align(4) (#bfi_y, [[Y]] : !cir.ptr<!u8i>, [[TWO]] : !s32i) -> !s32i
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// CIR: [[ZERO:%.*]] = cir.const #cir.int<0> : !s32i
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// CIR: [[Z:%.*]] = cir.get_member [[ALLOC]][2] {name = "z"} : !cir.ptr<!rec_demo> -> !cir.ptr<!u8i>
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// CIR: [[SET2:%.*]] = cir.set_bitfield align(4) (#bfi_z, [[Z]] : !cir.ptr<!u8i>, [[ZERO]] : !s32i) -> !s32i
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// CIR: cir.return
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// LLVM: define dso_local void @f
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// LLVM: [[ALLOC:%.*]] = alloca %union.demo, i64 1, align 4
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// LLVM: store i32 1, ptr [[ALLOC]], align 4
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// LLVM: [[BFLOAD:%.*]] = load i8, ptr [[ALLOC]], align 4
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// LLVM: [[CLEAR:%.*]] = and i8 [[BFLOAD]], -16
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// LLVM: [[SET:%.*]] = or i8 [[CLEAR]], 2
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// LLVM: store i8 [[SET]], ptr [[ALLOC]], align 4
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// LLVM: store i8 0, ptr [[ALLOC]], align 4
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// OGCG: define dso_local void @f
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// OGCG: [[ALLOC:%.*]] = alloca %union.demo, align 4
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// OGCG: store i32 1, ptr [[ALLOC]], align 4
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// OGCG: [[BFLOAD:%.*]] = load i8, ptr [[ALLOC]], align 4
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// OGCG: [[CLEAR:%.*]] = and i8 [[BFLOAD]], -16
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// OGCG: [[SET:%.*]] = or i8 [[CLEAR]], 2
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// OGCG: store i8 [[SET]], ptr [[ALLOC]], align 4
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// OGCG: store i8 0, ptr [[ALLOC]], align 4
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