6c3adaafe3
Currently arm_neon.h emits C-style casts to do vector type casts. This relies on implicit conversion between vector types to be enabled, which is currently deprecated behaviour and soon will disappear. To ensure NEON code will keep working afterwards, this patch changes all this vector type casts into bitcasts. Co-authored-by: Momchil Velikov <momchil.velikov@arm.com>
29 lines
1.4 KiB
C
29 lines
1.4 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 -triple arm64-apple-ios7 -target-feature +neon -ffreestanding -o - -emit-llvm %s | opt -S -passes=mem2reg | FileCheck %s
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// Test ARM64 SIMD vcreate intrinsics
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_neon.h>
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// CHECK-LABEL: define <2 x float> @test_vcreate_f32(
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// CHECK-SAME: i64 noundef [[A1:%.*]]) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[A1_ADDR:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[__RET:%.*]] = alloca <2 x float>, align 8
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// CHECK-NEXT: [[__PROMOTE:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[TMP:%.*]] = alloca <2 x float>, align 8
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// CHECK-NEXT: store i64 [[A1]], ptr [[A1_ADDR]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[A1_ADDR]], align 8
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// CHECK-NEXT: store i64 [[TMP0]], ptr [[__PROMOTE]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[__PROMOTE]], align 8
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// CHECK-NEXT: store <2 x float> [[TMP1]], ptr [[__RET]], align 8
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// CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[__RET]], align 8
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// CHECK-NEXT: store <2 x float> [[TMP2]], ptr [[TMP]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[TMP]], align 8
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// CHECK-NEXT: ret <2 x float> [[TMP3]]
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//
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float32x2_t test_vcreate_f32(uint64_t a1) {
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return vcreate_f32(a1);
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}
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