e13cbaca69
This is primarily meant to address the issue identified in #109182, around incorrect usage of `-fsycl-is-device`; we now have AMDGCN flavoured SPIR-V which retains the desired behaviour around the default AS and does not depend on the SYCL language being enabled to do so. Overall, there are three changes: 1. We unconditionally use the `SPIRDefIsGen` AS map for AMDGCNSPIRV target, as there is no case where the hack of setting default to private would be desirable, and it can be used for languages other than OCL/HIP; 2. We implement `SPIRVTargetCodeGenInfo::getGlobalVarAddressSpace` for SPIR-V in general, because otherwise using it from languages other than HIP or OpenCL would yield 0, incorrectly; 3. We remove the incorrect usage of `-fsycl-is-device`.
42 lines
2.0 KiB
C++
42 lines
2.0 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -o - %s | FileCheck %s
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// CHECK-LABEL: define spir_func void @_Z1fv(
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// CHECK-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[X:%.*]] = alloca half, align 2
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// CHECK-NEXT: [[Y:%.*]] = alloca half, align 2
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// CHECK-NEXT: [[Z:%.*]] = alloca half, align 2
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// CHECK-NEXT: [[X_ASCAST:%.*]] = addrspacecast ptr [[X]] to ptr addrspace(4)
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// CHECK-NEXT: [[Y_ASCAST:%.*]] = addrspacecast ptr [[Y]] to ptr addrspace(4)
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// CHECK-NEXT: [[Z_ASCAST:%.*]] = addrspacecast ptr [[Z]] to ptr addrspace(4)
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// CHECK-NEXT: [[TMP0:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
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// CHECK-NEXT: [[TMP1:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
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// CHECK-NEXT: [[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
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// CHECK-NEXT: store half [[ADD]], ptr addrspace(4) [[Z_ASCAST]], align 2
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// CHECK-NEXT: [[TMP2:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
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// CHECK-NEXT: [[TMP3:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
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// CHECK-NEXT: [[SUB:%.*]] = fsub half [[TMP2]], [[TMP3]]
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// CHECK-NEXT: store half [[SUB]], ptr addrspace(4) [[Z_ASCAST]], align 2
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// CHECK-NEXT: [[TMP4:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
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// CHECK-NEXT: [[TMP5:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
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// CHECK-NEXT: [[MUL:%.*]] = fmul half [[TMP4]], [[TMP5]]
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// CHECK-NEXT: store half [[MUL]], ptr addrspace(4) [[Z_ASCAST]], align 2
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// CHECK-NEXT: [[TMP6:%.*]] = load half, ptr addrspace(4) [[X_ASCAST]], align 2
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// CHECK-NEXT: [[TMP7:%.*]] = load half, ptr addrspace(4) [[Y_ASCAST]], align 2
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// CHECK-NEXT: [[DIV:%.*]] = fdiv half [[TMP6]], [[TMP7]]
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// CHECK-NEXT: store half [[DIV]], ptr addrspace(4) [[Z_ASCAST]], align 2
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// CHECK-NEXT: ret void
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//
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void f() {
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_Float16 x, y, z;
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z = x + y;
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z = x - y;
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z = x * y;
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z = x / y;
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}
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