d7e23bef6a
lldb-server had limited support for single-stepping through the lr/sc atomic sequence. This patch enhances that support for all possible atomic sequences. The previous version contained an incorrect regex pattern in the test, causing the riscv-specific test to run on other platforms. This reland fixes the regex (see lldb/test/API/riscv/step/TestSoftwareStep.py)
80 lines
3.2 KiB
Python
80 lines
3.2 KiB
Python
"""
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Test software step-inst, also known as instruction level single step, in risc-v atomic sequence.
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For more information about atomic sequences, see the RISC-V Unprivileged ISA specification.
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"""
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import lldb
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from lldbsuite.test.decorators import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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class TestSoftwareStep(TestBase):
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def do_sequence_test(self, filename, bkpt_name):
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source_file = filename + ".c"
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exe_file = filename + ".x"
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self.build(dictionary={"C_SOURCES": source_file, "EXE": exe_file})
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(target, process, cur_thread, bkpt) = lldbutil.run_to_name_breakpoint(
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self, bkpt_name, exe_name=exe_file
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)
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entry_pc = cur_thread.GetFrameAtIndex(0).GetPC()
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self.runCmd("thread step-inst")
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self.expect(
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"thread list",
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substrs=["stopped", "stop reason = instruction step into"],
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)
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pc = cur_thread.GetFrameAtIndex(0).GetPC()
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return pc - entry_pc
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@skipIf(archs=no_match("^rv.*"))
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def test_cas(self):
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"""
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This test verifies LLDB instruction step handling of a proper lr/sc pair.
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"""
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difference = self.do_sequence_test("main", "cas")
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self.assertEqual(difference, 0x1A)
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@skipIf(archs=no_match("^rv.*"))
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def test_branch_cas(self):
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"""
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LLDB cannot predict the actual state of registers within a critical section (i.e., inside an atomic
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sequence). Therefore, it should identify all forward branches inside the atomic sequence and set
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breakpoints at every jump address that lies beyond the end of the sequence (after the sc instruction).
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This ensures that if any such branch is taken, execution will pause at its target address.
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This test includes an lr/sc sequence containing an active forward branch with a jump address located
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after the end of the atomic section. LLDB should correctly stop at this branch's target address. The
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test is nearly identical to the previous one, except for the branch condition, which is inverted and
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will result in a taken jump.
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"""
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difference = self.do_sequence_test("branch", "branch_cas")
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self.assertEqual(difference, 0x1A)
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@skipIf(archs=no_match("^rv.*"))
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def test_incomplete_sequence_without_lr(self):
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"""
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This test verifies the behavior of a standalone sc instruction without a preceding lr. Since the sc
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lacks the required lr pairing, LLDB should treat it as a non-atomic store rather than part of an
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atomic sequence.
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"""
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difference = self.do_sequence_test(
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"incomplete_sequence_without_lr", "incomplete_cas"
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)
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self.assertEqual(difference, 0x4)
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@skipIf(archs=no_match("^rv.*"))
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def test_incomplete_sequence_without_sc(self):
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"""
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This test checks the behavior of a standalone lr instruction without a subsequent sc. Since the lr
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lacks its required sc counterpart, LLDB should treat it as a non-atomic load rather than part of an
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atomic sequence.
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"""
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difference = self.do_sequence_test(
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"incomplete_sequence_without_sc", "incomplete_cas"
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)
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self.assertEqual(difference, 0x4)
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