c27eded938
Summary of changes: - Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205). - Enable abs and neg modifiers for v_cndmask_b32_dpp (https://reviews.llvm.org/D135900). - Enable literal operands for permlane16/permlanex16 (https://reviews.llvm.org/D137332). - Enable omod modifiers for v_max3_f16, v_min3_f16, etc. (https://reviews.llvm.org/D139469). - Correct v_mov_b32_sdwa (it does not support abs and neg input modifiers yet). - Enable tfe modifier for MUBUF loads (https://reviews.llvm.org/D137783). - Enable image_gather4h (https://reviews.llvm.org/D130764). - Minor corrections and improvements.
29 lines
929 B
ReStructuredText
29 lines
929 B
ReStructuredText
..
|
|
**************************************************
|
|
* *
|
|
* Automatically generated file, do not edit! *
|
|
* *
|
|
**************************************************
|
|
|
|
.. _amdgpu_synid_gfx1030_vsrc_ba3116:
|
|
|
|
vsrc
|
|
====
|
|
|
|
Data to copy to export buffers. This is an optional operand. Must be specified as :ref:`off<amdgpu_synid_off>` if not used.
|
|
|
|
The :ref:`compr<amdgpu_synid_compr>` modifier indicates the use of compressed (16-bit) data, thus decreasing the number of source operands from 4 to 2:
|
|
|
|
* src0 and src1 must specify the first register (or :ref:`off<amdgpu_synid_off>`).
|
|
* src2 and src3 must specify the second register (or :ref:`off<amdgpu_synid_off>`).
|
|
|
|
An example:
|
|
|
|
.. parsed-literal::
|
|
|
|
exp mrtz v3, v3, off, off compr
|
|
|
|
*Size:* 1 dword.
|
|
|
|
*Operands:* :ref:`v<amdgpu_synid_v>`, :ref:`off<amdgpu_synid_off>`
|