
This reverts partially this commit 0b73b5af60f2c544892b9dd68b4fa43eeff52fc1. This is not a clear revert because other changes already landed. CFI directives like `.cfi_negate_ra_state` must be emitted after the instruction. If the execution is stopped before the `paciasp` instruction is executed the debugger/unwinder would try to authenticated the return address as the `.cfi_negate_ra_state` already indicates it got signed. fixes: #137802
281 lines
10 KiB
C++
281 lines
10 KiB
C++
//===-- AArch64PointerAuth.cpp -- Harden code using PAuth ------------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64PointerAuth.h"
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#include "AArch64.h"
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#include "AArch64InstrInfo.h"
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#include "AArch64MachineFunctionInfo.h"
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#include "AArch64Subtarget.h"
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#include "llvm/CodeGen/CFIInstBuilder.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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using namespace llvm;
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using namespace llvm::AArch64PAuth;
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#define AARCH64_POINTER_AUTH_NAME "AArch64 Pointer Authentication"
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namespace {
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class AArch64PointerAuth : public MachineFunctionPass {
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public:
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static char ID;
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AArch64PointerAuth() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return AARCH64_POINTER_AUTH_NAME; }
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private:
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const AArch64Subtarget *Subtarget = nullptr;
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const AArch64InstrInfo *TII = nullptr;
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void signLR(MachineFunction &MF, MachineBasicBlock::iterator MBBI) const;
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void authenticateLR(MachineFunction &MF,
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MachineBasicBlock::iterator MBBI) const;
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bool checkAuthenticatedLR(MachineBasicBlock::iterator TI) const;
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};
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} // end anonymous namespace
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INITIALIZE_PASS(AArch64PointerAuth, "aarch64-ptrauth",
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AARCH64_POINTER_AUTH_NAME, false, false)
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FunctionPass *llvm::createAArch64PointerAuthPass() {
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return new AArch64PointerAuth();
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}
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char AArch64PointerAuth::ID = 0;
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static void emitPACSymOffsetIntoX16(const TargetInstrInfo &TII,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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MCSymbol *PACSym) {
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BuildMI(MBB, I, DL, TII.get(AArch64::ADRP), AArch64::X16)
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.addSym(PACSym, AArch64II::MO_PAGE);
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BuildMI(MBB, I, DL, TII.get(AArch64::ADDXri), AArch64::X16)
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.addReg(AArch64::X16)
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.addSym(PACSym, AArch64II::MO_PAGEOFF | AArch64II::MO_NC)
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.addImm(0);
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}
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// Where PAuthLR support is not known at compile time, it is supported using
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// PACM. PACM is in the hint space so has no effect when PAuthLR is not
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// supported by the hardware, but will alter the behaviour of PACI*SP, AUTI*SP
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// and RETAA/RETAB if the hardware supports PAuthLR.
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static void BuildPACM(const AArch64Subtarget &Subtarget, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, DebugLoc DL,
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MachineInstr::MIFlag Flags, MCSymbol *PACSym = nullptr) {
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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auto &MFnI = *MBB.getParent()->getInfo<AArch64FunctionInfo>();
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// Offset to PAC*SP using ADRP + ADD.
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if (PACSym) {
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assert(Flags == MachineInstr::FrameDestroy);
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emitPACSymOffsetIntoX16(*TII, MBB, MBBI, DL, PACSym);
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}
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// Only emit PACM if -mbranch-protection has +pc and the target does not
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// have feature +pauth-lr.
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if (MFnI.branchProtectionPAuthLR() && !Subtarget.hasPAuthLR())
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACM)).setMIFlag(Flags);
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}
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static void emitPACCFI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineInstr::MIFlag Flags, bool EmitCFI) {
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if (!EmitCFI)
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return;
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auto &MF = *MBB.getParent();
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auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
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CFIInstBuilder CFIBuilder(MBB, MBBI, Flags);
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MFnI.branchProtectionPAuthLR() ? CFIBuilder.buildNegateRAStateWithPC()
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: CFIBuilder.buildNegateRAState();
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}
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void AArch64PointerAuth::signLR(MachineFunction &MF,
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MachineBasicBlock::iterator MBBI) const {
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auto &MFnI = *MF.getInfo<AArch64FunctionInfo>();
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bool UseBKey = MFnI.shouldSignWithBKey();
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bool EmitCFI = MFnI.needsDwarfUnwindInfo(MF);
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bool NeedsWinCFI = MF.hasWinCFI();
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MachineBasicBlock &MBB = *MBBI->getParent();
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// Debug location must be unknown, see AArch64FrameLowering::emitPrologue.
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DebugLoc DL;
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if (UseBKey) {
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY))
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.setMIFlag(MachineInstr::FrameSetup);
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}
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// PAuthLR authentication instructions need to know the value of PC at the
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// point of signing (PACI*).
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if (MFnI.branchProtectionPAuthLR()) {
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MCSymbol *PACSym = MF.getContext().createTempSymbol();
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MFnI.setSigningInstrLabel(PACSym);
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}
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// No SEH opcode for this one; it doesn't materialize into an
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// instruction on Windows.
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if (MFnI.branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
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emitPACCFI(MBB, MBBI, MachineInstr::FrameSetup, EmitCFI);
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BuildMI(MBB, MBBI, DL,
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TII->get(MFnI.shouldSignWithBKey() ? AArch64::PACIBSPPC
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: AArch64::PACIASPPC))
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.setMIFlag(MachineInstr::FrameSetup)
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->setPreInstrSymbol(MF, MFnI.getSigningInstrLabel());
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} else {
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BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup);
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if (MFnI.branchProtectionPAuthLR())
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emitPACCFI(MBB, MBBI, MachineInstr::FrameSetup, EmitCFI);
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BuildMI(MBB, MBBI, DL,
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TII->get(MFnI.shouldSignWithBKey() ? AArch64::PACIBSP
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: AArch64::PACIASP))
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.setMIFlag(MachineInstr::FrameSetup)
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->setPreInstrSymbol(MF, MFnI.getSigningInstrLabel());
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if (!MFnI.branchProtectionPAuthLR())
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emitPACCFI(MBB, MBBI, MachineInstr::FrameSetup, EmitCFI);
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}
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if (!EmitCFI && NeedsWinCFI) {
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR))
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.setMIFlag(MachineInstr::FrameSetup);
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}
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}
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void AArch64PointerAuth::authenticateLR(
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MachineFunction &MF, MachineBasicBlock::iterator MBBI) const {
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const AArch64FunctionInfo *MFnI = MF.getInfo<AArch64FunctionInfo>();
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bool UseBKey = MFnI->shouldSignWithBKey();
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bool EmitAsyncCFI = MFnI->needsAsyncDwarfUnwindInfo(MF);
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bool NeedsWinCFI = MF.hasWinCFI();
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MachineBasicBlock &MBB = *MBBI->getParent();
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DebugLoc DL = MBBI->getDebugLoc();
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// MBBI points to a PAUTH_EPILOGUE instruction to be replaced and
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// TI points to a terminator instruction that may or may not be combined.
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// Note that inserting new instructions "before MBBI" and "before TI" is
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// not the same because if ShadowCallStack is enabled, its instructions
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// are placed between MBBI and TI.
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MachineBasicBlock::iterator TI = MBB.getFirstInstrTerminator();
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// The AUTIASP instruction assembles to a hint instruction before v8.3a so
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// this instruction can safely used for any v8a architecture.
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// From v8.3a onwards there are optimised authenticate LR and return
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// instructions, namely RETA{A,B}, that can be used instead. In this case the
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// DW_CFA_AARCH64_negate_ra_state can't be emitted.
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bool TerminatorIsCombinable =
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TI != MBB.end() && TI->getOpcode() == AArch64::RET;
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MCSymbol *PACSym = MFnI->getSigningInstrLabel();
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if (Subtarget->hasPAuth() && TerminatorIsCombinable && !NeedsWinCFI &&
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!MF.getFunction().hasFnAttribute(Attribute::ShadowCallStack)) {
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if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
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assert(PACSym && "No PAC instruction to refer to");
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emitPACSymOffsetIntoX16(*TII, MBB, MBBI, DL, PACSym);
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BuildMI(MBB, TI, DL,
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TII->get(UseBKey ? AArch64::RETABSPPCi : AArch64::RETAASPPCi))
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.addSym(PACSym)
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.copyImplicitOps(*MBBI)
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.setMIFlag(MachineInstr::FrameDestroy);
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} else {
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BuildPACM(*Subtarget, MBB, TI, DL, MachineInstr::FrameDestroy, PACSym);
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BuildMI(MBB, TI, DL, TII->get(UseBKey ? AArch64::RETAB : AArch64::RETAA))
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.copyImplicitOps(*MBBI)
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.setMIFlag(MachineInstr::FrameDestroy);
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}
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MBB.erase(TI);
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} else {
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if (MFnI->branchProtectionPAuthLR() && Subtarget->hasPAuthLR()) {
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assert(PACSym && "No PAC instruction to refer to");
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emitPACSymOffsetIntoX16(*TII, MBB, MBBI, DL, PACSym);
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emitPACCFI(MBB, MBBI, MachineInstr::FrameDestroy, EmitAsyncCFI);
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BuildMI(MBB, MBBI, DL,
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TII->get(UseBKey ? AArch64::AUTIBSPPCi : AArch64::AUTIASPPCi))
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.addSym(PACSym)
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.setMIFlag(MachineInstr::FrameDestroy);
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} else {
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BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameDestroy, PACSym);
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if (MFnI->branchProtectionPAuthLR())
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emitPACCFI(MBB, MBBI, MachineInstr::FrameDestroy, EmitAsyncCFI);
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BuildMI(MBB, MBBI, DL,
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TII->get(UseBKey ? AArch64::AUTIBSP : AArch64::AUTIASP))
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.setMIFlag(MachineInstr::FrameDestroy);
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if (!MFnI->branchProtectionPAuthLR())
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emitPACCFI(MBB, MBBI, MachineInstr::FrameDestroy, EmitAsyncCFI);
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}
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if (NeedsWinCFI) {
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BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR))
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.setMIFlag(MachineInstr::FrameDestroy);
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}
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}
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}
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unsigned llvm::AArch64PAuth::getCheckerSizeInBytes(AuthCheckMethod Method) {
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switch (Method) {
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case AuthCheckMethod::None:
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return 0;
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case AuthCheckMethod::DummyLoad:
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return 4;
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case AuthCheckMethod::HighBitsNoTBI:
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return 12;
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case AuthCheckMethod::XPACHint:
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case AuthCheckMethod::XPAC:
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return 20;
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}
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llvm_unreachable("Unknown AuthCheckMethod enum");
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}
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bool AArch64PointerAuth::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<AArch64Subtarget>();
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TII = Subtarget->getInstrInfo();
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SmallVector<MachineBasicBlock::instr_iterator> PAuthPseudoInstrs;
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bool Modified = false;
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for (auto &MBB : MF) {
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for (auto &MI : MBB) {
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switch (MI.getOpcode()) {
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default:
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break;
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case AArch64::PAUTH_PROLOGUE:
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case AArch64::PAUTH_EPILOGUE:
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PAuthPseudoInstrs.push_back(MI.getIterator());
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break;
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}
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}
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}
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for (auto It : PAuthPseudoInstrs) {
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switch (It->getOpcode()) {
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case AArch64::PAUTH_PROLOGUE:
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signLR(MF, It);
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break;
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case AArch64::PAUTH_EPILOGUE:
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authenticateLR(MF, It);
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break;
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default:
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llvm_unreachable("Unhandled opcode");
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}
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It->eraseFromParent();
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Modified = true;
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}
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return Modified;
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}
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