80f3b376b3
When either one of the operands is all ones in high or low parts, splitting these opens up other opportunities for combines. One of two new instructions will either be removed or become a simple copy.
224 lines
9.9 KiB
TableGen
224 lines
9.9 KiB
TableGen
//=- AMDGPUCombine.td - Define AMDGPU Combine Rules ----------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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// TODO: This really belongs after legalization after scalarization.
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def fmin_fmax_legacy_matchdata : GIDefMatchData<"FMinFMaxLegacyInfo">;
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let Predicates = [HasFminFmaxLegacy] in
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def fcmp_select_to_fmin_fmax_legacy : GICombineRule<
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(defs root:$select, fmin_fmax_legacy_matchdata:$matchinfo),
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(match (G_FCMP $cond, $pred, $lhs, $rhs):$fcmp,
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(G_SELECT f32:$dst, $cond, $true, $false):$select,
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[{ return matchFMinFMaxLegacy(*${select}, *${fcmp}, ${matchinfo}); }]),
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(apply [{ applySelectFCmpToFMinFMaxLegacy(*${select}, ${matchinfo}); }])>;
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def uchar_to_float : GICombineRule<
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(defs root:$itofp),
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(match (wip_match_opcode G_UITOFP, G_SITOFP):$itofp,
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[{ return matchUCharToFloat(*${itofp}); }]),
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(apply [{ applyUCharToFloat(*${itofp}); }])>;
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def rcp_sqrt_to_rsq : GICombineRule<
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(defs root:$rcp, build_fn_matchinfo:$matchinfo),
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(match (wip_match_opcode G_INTRINSIC, G_FSQRT):$rcp,
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[{ return matchRcpSqrtToRsq(*${rcp}, ${matchinfo}); }]),
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(apply [{ Helper.applyBuildFn(*${rcp}, ${matchinfo}); }])>;
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def fdiv_by_sqrt_to_rsq_f16 : GICombineRule<
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(defs root:$root),
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(match (G_FSQRT f16:$sqrt, $x, (MIFlags FmContract)),
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(G_FDIV f16:$dst, $y, $sqrt, (MIFlags FmContract)):$root,
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[{ return matchFDivSqrtToRsqF16(*${root}); }]),
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(apply [{ applyFDivSqrtToRsqF16(*${root}, ${x}.getReg()); }])>;
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def cvt_f32_ubyteN_matchdata : GIDefMatchData<"CvtF32UByteMatchInfo">;
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def cvt_f32_ubyteN : GICombineRule<
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(defs root:$cvt_f32_ubyteN, cvt_f32_ubyteN_matchdata:$matchinfo),
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(match (wip_match_opcode G_AMDGPU_CVT_F32_UBYTE0,
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G_AMDGPU_CVT_F32_UBYTE1,
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G_AMDGPU_CVT_F32_UBYTE2,
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G_AMDGPU_CVT_F32_UBYTE3):$cvt_f32_ubyteN,
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[{ return matchCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }]),
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(apply [{ applyCvtF32UByteN(*${cvt_f32_ubyteN}, ${matchinfo}); }])>;
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def clamp_i64_to_i16_matchdata : GIDefMatchData<"ClampI64ToI16MatchInfo">;
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def clamp_i64_to_i16 : GICombineRule<
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(defs root:$clamp_i64_to_i16, clamp_i64_to_i16_matchdata:$matchinfo),
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(match (wip_match_opcode G_TRUNC):$clamp_i64_to_i16,
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[{ return matchClampI64ToI16(*${clamp_i64_to_i16}, MRI, MF, ${matchinfo}); }]),
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(apply [{ applyClampI64ToI16(*${clamp_i64_to_i16}, ${matchinfo}); }])>;
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def med3_matchdata : GIDefMatchData<"Med3MatchInfo">;
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def int_minmax_to_med3 : GICombineRule<
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(defs root:$min_or_max, med3_matchdata:$matchinfo),
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(match (wip_match_opcode G_SMAX,
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G_SMIN,
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G_UMAX,
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G_UMIN):$min_or_max,
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[{ return matchIntMinMaxToMed3(*${min_or_max}, ${matchinfo}); }]),
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(apply [{ applyMed3(*${min_or_max}, ${matchinfo}); }])>;
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def fp_minmax_to_med3 : GICombineRule<
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(defs root:$min_or_max, med3_matchdata:$matchinfo),
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(match (wip_match_opcode G_FMAXNUM,
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G_FMINNUM,
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G_FMAXNUM_IEEE,
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G_FMINNUM_IEEE):$min_or_max,
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[{ return matchFPMinMaxToMed3(*${min_or_max}, ${matchinfo}); }]),
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(apply [{ applyMed3(*${min_or_max}, ${matchinfo}); }])>;
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def fp_minmax_to_clamp : GICombineRule<
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(defs root:$min_or_max, register_matchinfo:$matchinfo),
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(match (wip_match_opcode G_FMAXNUM,
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G_FMINNUM,
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G_FMAXNUM_IEEE,
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G_FMINNUM_IEEE):$min_or_max,
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[{ return matchFPMinMaxToClamp(*${min_or_max}, ${matchinfo}); }]),
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(apply [{ applyClamp(*${min_or_max}, ${matchinfo}); }])>;
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def fmed3_intrinsic_to_clamp : GICombineRule<
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(defs root:$fmed3, register_matchinfo:$matchinfo),
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(match (wip_match_opcode G_AMDGPU_FMED3):$fmed3,
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[{ return matchFPMed3ToClamp(*${fmed3}, ${matchinfo}); }]),
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(apply [{ applyClamp(*${fmed3}, ${matchinfo}); }])>;
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def remove_fcanonicalize : GICombineRule<
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(defs root:$fcanonicalize, register_matchinfo:$matchinfo),
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(match (wip_match_opcode G_FCANONICALIZE):$fcanonicalize,
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[{ return matchRemoveFcanonicalize(*${fcanonicalize}, ${matchinfo}); }]),
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(apply [{ Helper.replaceSingleDefInstWithReg(*${fcanonicalize}, ${matchinfo}); }])>;
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def foldable_fneg_matchdata : GIDefMatchData<"MachineInstr *">;
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def foldable_fneg : GICombineRule<
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(defs root:$ffn, foldable_fneg_matchdata:$matchinfo),
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(match (wip_match_opcode G_FNEG):$ffn,
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[{ return Helper.matchFoldableFneg(*${ffn}, ${matchinfo}); }]),
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(apply [{ Helper.applyFoldableFneg(*${ffn}, ${matchinfo}); }])>;
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// Detects s_mul_u64 instructions whose higher bits are zero/sign extended.
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def smulu64 : GICombineRule<
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(defs root:$smul, unsigned_matchinfo:$matchinfo),
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(match (wip_match_opcode G_MUL):$smul,
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[{ return matchCombine_s_mul_u64(*${smul}, ${matchinfo}); }]),
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(apply [{ Helper.replaceOpcodeWith(*${smul}, ${matchinfo}); }])>;
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def sign_exension_in_reg_matchdata : GIDefMatchData<"std::pair<MachineInstr *, unsigned>">;
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def sign_extension_in_reg : GICombineRule<
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(defs root:$sign_inreg, sign_exension_in_reg_matchdata:$matchinfo),
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(match (wip_match_opcode G_SEXT_INREG):$sign_inreg,
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[{ return matchCombineSignExtendInReg(*${sign_inreg}, ${matchinfo}); }]),
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(apply [{ applyCombineSignExtendInReg(*${sign_inreg}, ${matchinfo}); }])>;
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// Do the following combines :
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// fmul x, select(y, A, B) -> fldexp (x, select i32 (y, a, b))
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// fmul x, select(y, -A, -B) -> fldexp ((fneg x), select i32 (y, a, b))
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def combine_fmul_with_select_to_fldexp : GICombineRule<
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(defs root:$root, build_fn_matchinfo:$matchinfo),
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(match (G_FMUL $dst, $x, $select):$root,
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(G_SELECT $select, $y, $A, $B):$sel,
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[{ return Helper.matchCombineFmulWithSelectToFldexp(*${root}, *${sel}, ${matchinfo}); }]),
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(apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>;
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// (shift x, (zext amt)) -> (shift x, (and (anyext amt), mask)
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//
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// The pattern is longer, but is better for matching during ISel.
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class canonicalize_zext_shift_amt<Instruction opc> : GICombineRule<
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(defs root:$dst),
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(match (G_ZEXT $amt, $amtsrc):$zext,
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(opc $dst, $src, $amt):$shift),
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(apply [{ applyCanonicalizeZextShiftAmt(*${shift}, *${zext}); }])>;
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def canonicalize_zext_lshr : canonicalize_zext_shift_amt<G_LSHR>;
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def canonicalize_zext_ashr : canonicalize_zext_shift_amt<G_ASHR>;
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def canonicalize_zext_shl : canonicalize_zext_shift_amt<G_SHL>;
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def zext_of_shift_amount_combines : GICombineGroup<[
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canonicalize_zext_lshr, canonicalize_zext_ashr, canonicalize_zext_shl
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]>;
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// (and/or i64:x, i64:y) -> i64:(merge (and/or lo_32(x), lo_32(y)), (and/or hi_32(x), hi_32(y)))
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// when either x or y is all ones in low or high parts
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class combine_binop_s64_with_s32_mask<Instruction opcode> : GICombineRule<
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(defs root:$dst),
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(match (opcode $dst, i64:$x, i64:$y):$dst,
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[{ return Helper.matchConstantIs32BitMask(${x}.getReg()) ||
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Helper.matchConstantIs32BitMask(${y}.getReg()); }]),
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(apply (G_UNMERGE_VALUES i32:$x_lo, i32:$x_hi, $x),
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(G_UNMERGE_VALUES i32:$y_lo, i32:$y_hi, $y),
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(opcode i32:$lo, $x_lo, $y_lo),
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(opcode i32:$hi, $x_hi, $y_hi),
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(G_MERGE_VALUES $dst, $lo, $hi))>;
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def combine_or_s64_with_s32_mask : combine_binop_s64_with_s32_mask<G_OR>;
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def combine_and_s64_with_s32_mask : combine_binop_s64_with_s32_mask<G_AND>;
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def binop_s64_with_s32_mask_combines : GICombineGroup<[
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combine_or_s64_with_s32_mask, combine_and_s64_with_s32_mask
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]>;
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let Predicates = [Has16BitInsts, NotHasMed3_16] in {
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// For gfx8, expand f16-fmed3-as-f32 into a min/max f16 sequence. This
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// saves one instruction compared to the promotion.
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//
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// FIXME: Should have ComplexPattern like in/out matchers
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//
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// FIXME: We should be able to match either G_AMDGPU_FMED3 or
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// G_INTRINSIC @llvm.amdgcn.fmed3. Currently the legalizer will
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// replace the intrinsic with G_AMDGPU_FMED3 since we can't write a
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// pattern to match it.
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def expand_promoted_fmed3 : GICombineRule<
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(defs root:$fptrunc_dst),
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(match (G_FPTRUNC $fptrunc_dst, $fmed3_dst):$fptrunc,
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(G_AMDGPU_FMED3 $fmed3_dst, $src0, $src1, $src2),
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[{ return Helper.matchExpandPromotedF16FMed3(*${fptrunc}, ${src0}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }]),
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(apply [{ Helper.applyExpandPromotedF16FMed3(*${fptrunc}, ${src0}.getReg(), ${src1}.getReg(), ${src2}.getReg()); }])
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>;
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} // End Predicates = [NotHasMed3_16]
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// Combines which should only apply on SI/CI
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def gfx6gfx7_combines : GICombineGroup<[fcmp_select_to_fmin_fmax_legacy]>;
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// Combines which should only apply on VI
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def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
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def AMDGPUPreLegalizerCombiner: GICombiner<
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"AMDGPUPreLegalizerCombinerImpl",
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[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
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foldable_fneg, combine_shuffle_vector_to_build_vector,
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binop_s64_with_s32_mask_combines]> {
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let CombineAllMethodName = "tryCombineAllImpl";
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}
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def AMDGPUPostLegalizerCombiner: GICombiner<
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"AMDGPUPostLegalizerCombinerImpl",
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[all_combines, gfx6gfx7_combines, gfx8_combines, combine_fmul_with_select_to_fldexp,
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uchar_to_float, cvt_f32_ubyteN, remove_fcanonicalize, foldable_fneg,
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rcp_sqrt_to_rsq, fdiv_by_sqrt_to_rsq_f16, sign_extension_in_reg, smulu64,
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binop_s64_with_s32_mask_combines]> {
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let CombineAllMethodName = "tryCombineAllImpl";
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}
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def AMDGPURegBankCombiner : GICombiner<
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"AMDGPURegBankCombinerImpl",
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[unmerge_merge, unmerge_cst, unmerge_undef,
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zext_trunc_fold, int_minmax_to_med3, ptr_add_immed_chain,
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fp_minmax_to_clamp, fp_minmax_to_med3, fmed3_intrinsic_to_clamp,
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identity_combines, redundant_and, constant_fold_cast_op,
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cast_of_cast_combines, sext_trunc, zext_of_shift_amount_combines]> {
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}
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