3564cfa211
Add rules for G_AMDGPU_BUFFER_LOAD and implement waterfall lowering for divergent operands that must be sgpr.
130 lines
4.9 KiB
C++
130 lines
4.9 KiB
C++
//===- AMDGPURegBankLegalizeHelper ------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGBANKLEGALIZEHELPER_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGBANKLEGALIZEHELPER_H
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#include "AMDGPURegBankLegalizeRules.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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class MachineIRBuilder;
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namespace AMDGPU {
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// Receives list of RegBankLLTMappingApplyID and applies register banks on all
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// operands. It is user's responsibility to provide RegBankLLTMappingApplyIDs
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// for all register operands, there is no need to specify NonReg for trailing
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// imm operands. This finishes selection of register banks if there is no need
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// to replace instruction. In other case InstApplyMethod will create new
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// instruction(s).
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class RegBankLegalizeHelper {
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const GCNSubtarget &ST;
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MachineIRBuilder &B;
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MachineRegisterInfo &MRI;
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const MachineUniformityInfo &MUI;
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const RegisterBankInfo &RBI;
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const RegBankLegalizeRules &RBLRules;
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const bool IsWave32;
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const RegisterBank *SgprRB;
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const RegisterBank *VgprRB;
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const RegisterBank *VccRB;
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static constexpr LLT S1 = LLT::scalar(1);
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static constexpr LLT S16 = LLT::scalar(16);
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static constexpr LLT S32 = LLT::scalar(32);
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static constexpr LLT S64 = LLT::scalar(64);
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static constexpr LLT S96 = LLT::scalar(96);
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static constexpr LLT S128 = LLT::scalar(128);
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static constexpr LLT S256 = LLT::scalar(256);
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static constexpr LLT V2S16 = LLT::fixed_vector(2, 16);
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static constexpr LLT V4S16 = LLT::fixed_vector(4, 16);
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static constexpr LLT V6S16 = LLT::fixed_vector(6, 16);
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static constexpr LLT V8S16 = LLT::fixed_vector(8, 16);
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static constexpr LLT V16S16 = LLT::fixed_vector(16, 16);
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static constexpr LLT V32S16 = LLT::fixed_vector(32, 16);
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static constexpr LLT V2S32 = LLT::fixed_vector(2, 32);
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static constexpr LLT V3S32 = LLT::fixed_vector(3, 32);
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static constexpr LLT V4S32 = LLT::fixed_vector(4, 32);
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static constexpr LLT V6S32 = LLT::fixed_vector(6, 32);
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static constexpr LLT V7S32 = LLT::fixed_vector(7, 32);
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static constexpr LLT V8S32 = LLT::fixed_vector(8, 32);
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static constexpr LLT V16S32 = LLT::fixed_vector(16, 32);
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static constexpr LLT V2S64 = LLT::fixed_vector(2, 64);
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static constexpr LLT V3S64 = LLT::fixed_vector(3, 64);
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static constexpr LLT V4S64 = LLT::fixed_vector(4, 64);
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static constexpr LLT V8S64 = LLT::fixed_vector(8, 64);
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static constexpr LLT V16S64 = LLT::fixed_vector(16, 64);
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static constexpr LLT P1 = LLT::pointer(1, 64);
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static constexpr LLT P4 = LLT::pointer(4, 64);
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static constexpr LLT P6 = LLT::pointer(6, 32);
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MachineRegisterInfo::VRegAttrs SgprRB_S32 = {SgprRB, S32};
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MachineRegisterInfo::VRegAttrs VgprRB_S32 = {VgprRB, S32};
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MachineRegisterInfo::VRegAttrs VccRB_S1 = {VccRB, S1};
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public:
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RegBankLegalizeHelper(MachineIRBuilder &B, const MachineUniformityInfo &MUI,
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const RegisterBankInfo &RBI,
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const RegBankLegalizeRules &RBLRules);
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void findRuleAndApplyMapping(MachineInstr &MI);
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// Manual apply helpers.
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void applyMappingPHI(MachineInstr &MI);
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void applyMappingTrivial(MachineInstr &MI);
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private:
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bool executeInWaterfallLoop(MachineIRBuilder &B,
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iterator_range<MachineBasicBlock::iterator> Range,
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SmallSet<Register, 4> &SgprOperandRegs);
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LLT getTyFromID(RegBankLLTMappingApplyID ID);
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LLT getBTyFromID(RegBankLLTMappingApplyID ID, LLT Ty);
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const RegisterBank *getRegBankFromID(RegBankLLTMappingApplyID ID);
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void
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applyMappingDst(MachineInstr &MI, unsigned &OpIdx,
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const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs);
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void
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applyMappingSrc(MachineInstr &MI, unsigned &OpIdx,
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const SmallVectorImpl<RegBankLLTMappingApplyID> &MethodIDs,
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SmallSet<Register, 4> &SgprWaterfallOperandRegs);
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void splitLoad(MachineInstr &MI, ArrayRef<LLT> LLTBreakdown,
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LLT MergeTy = LLT());
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void widenLoad(MachineInstr &MI, LLT WideTy, LLT MergeTy = LLT());
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void lower(MachineInstr &MI, const RegBankLLTMapping &Mapping,
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SmallSet<Register, 4> &SgprWaterfallOperandRegs);
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void lowerVccExtToSel(MachineInstr &MI);
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std::pair<Register, Register> unpackZExt(Register Reg);
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std::pair<Register, Register> unpackSExt(Register Reg);
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std::pair<Register, Register> unpackAExt(Register Reg);
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void lowerUnpackBitShift(MachineInstr &MI);
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void lowerV_BFE(MachineInstr &MI);
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void lowerS_BFE(MachineInstr &MI);
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void lowerSplitTo32(MachineInstr &MI);
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void lowerSplitTo32Select(MachineInstr &MI);
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void lowerSplitTo32SExtInReg(MachineInstr &MI);
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};
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} // end namespace AMDGPU
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} // end namespace llvm
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#endif
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