290 lines
12 KiB
TableGen
290 lines
12 KiB
TableGen
//===-- VOPDInstructions.td - Vector Instruction Definitions --------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Encodings
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//===----------------------------------------------------------------------===//
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class VOPDe<bits<4> opX, bits<5> opY> : Enc64 {
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bits<9> src0X;
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bits<8> vsrc1X;
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bits<8> vdstX;
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bits<9> src0Y;
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bits<8> vsrc1Y;
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bits<8> vdstY;
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let Inst{8-0} = src0X;
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let Inst{16-9} = vsrc1X;
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let Inst{21-17} = opY;
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let Inst{25-22} = opX;
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let Inst{31-26} = 0x32; // encoding
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let Inst{40-32} = src0Y;
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let Inst{48-41} = vsrc1Y;
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let Inst{55-49} = vdstY{7-1};
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let Inst{63-56} = vdstX;
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}
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class VOPD_MADKe<bits<4> opX, bits<5> opY> : Enc96 {
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bits<9> src0X;
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bits<8> vsrc1X;
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bits<8> vdstX;
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bits<9> src0Y;
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bits<8> vsrc1Y;
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bits<8> vdstY;
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bits<32> imm;
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let Inst{8-0} = src0X;
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let Inst{16-9} = vsrc1X;
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let Inst{21-17} = opY;
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let Inst{25-22} = opX;
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let Inst{31-26} = 0x32; // encoding
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let Inst{40-32} = src0Y;
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let Inst{48-41} = vsrc1Y;
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let Inst{55-49} = vdstY{7-1};
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let Inst{63-56} = vdstX;
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let Inst{95-64} = imm;
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}
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class VOPD3e<bits<6> opX, bits<6> opY, VOP_Pseudo VDX, VOP_Pseudo VDY> : Enc96 {
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bits<9> src0X;
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bits<8> vsrc1X;
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bits<8> vsrc2X;
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bits<8> vdstX;
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bits<9> src0Y;
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bits<8> vsrc1Y;
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bits<8> vsrc2Y;
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bits<8> vdstY;
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// neg modifiers
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bit src0X_modifiers;
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bit src0Y_modifiers;
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bit vsrc1X_modifiers;
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bit vsrc1Y_modifiers;
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bit vsrc2X_modifiers;
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bit vsrc2Y_modifiers;
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bits<8> bitop3;
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let Inst{8-0} = src0X;
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let Inst{17-12} = opY;
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let Inst{23-18} = opX;
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let Inst{31-24} = 0xcf; // encoding
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let Inst{40-32} = src0Y;
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let Inst{41} = !if(VDX.Pfl.HasModifiers, src0X_modifiers, 0);
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let Inst{42} = !if(!and(VDX.Pfl.HasSrc1, VDX.Pfl.HasModifiers), vsrc1X_modifiers, 0);
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let Inst{43} = !if(!and(VDX.Pfl.HasVOPD3Src2, VDX.Pfl.HasModifiers), vsrc2X_modifiers, 0);
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let Inst{44} = !if(VDY.Pfl.HasModifiers, src0Y_modifiers, 0);
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let Inst{45} = !if(!and(VDY.Pfl.HasSrc1, VDY.Pfl.HasModifiers), vsrc1Y_modifiers, 0);
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let Inst{46} = !if(!and(VDY.Pfl.HasVOPD3Src2, VDY.Pfl.HasModifiers), vsrc2Y_modifiers, 0);
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let Inst{55-48} = !if(!eq(!find(VDX.Pfl.AsmVOPD3X, "$vsrc1X"), -1), 0, vsrc1X);
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// Despite the vsrc operand name, SGPRs can be used for vsrc2X for
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// V_DUAL_CNDMASK_B32
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let Inst{63-56} = !if(!eq(!find(VDX.Pfl.AsmVOPD3X, "$vsrc2X"), -1), 0, vsrc2X);
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let Inst{71-64} = vdstX;
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let Inst{79-72} = !if(!eq(!find(VDY.Pfl.AsmVOPD3Y, "$vsrc1Y"), -1), 0, vsrc1Y);
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let Inst{87-80} = !if(!ne(!find(VDY.Pfl.AsmVOPD3Y, "bitop"), -1), bitop3,
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!if(!eq(!find(VDY.Pfl.AsmVOPD3Y, "$vsrc2Y"), -1), 0, vsrc2Y));
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let Inst{95-88} = vdstY;
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}
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//===----------------------------------------------------------------------===//
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// VOPD classes
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//===----------------------------------------------------------------------===//
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class GFXGenD<GFXGen Gen, list<string> DXPseudos, list<string> DYPseudos,
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Predicate subtargetPred = Gen.AssemblerPredicate> :
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GFXGen<Gen.AssemblerPredicate, Gen.DecoderNamespace, Gen.Suffix,
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Gen.Subtarget> {
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list<string> VOPDXPseudos = DXPseudos;
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list<string> VOPDYPseudos = DYPseudos;
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Predicate SubtargetPredicate = subtargetPred;
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}
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class VOPD_Base<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
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VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
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: VOPAnyCommon<outs, ins, asm, []>,
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VOP<NAME>,
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SIMCInstr<NAME, Gen.Subtarget> {
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// Fields for table indexing
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Instruction Opcode = !cast<Instruction>(NAME);
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bits<6> OpX = XasVC.VOPDOp;
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bits<6> OpY = YasVC.VOPDOp;
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bits<4> SubTgt = Gen.Subtarget;
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let VALU = 1;
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let DecoderNamespace = Gen.DecoderNamespace;
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let AssemblerPredicate = Gen.AssemblerPredicate;
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let WaveSizePredicate = isWave32;
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let isCodeGenOnly = 0;
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let SubtargetPredicate = Gen.SubtargetPredicate;
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let AsmMatchConverter = "cvtVOPD";
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let Size = 8;
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let ReadsModeReg = !or(VDX.ReadsModeReg, VDY.ReadsModeReg);
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let mayRaiseFPException = ReadsModeReg;
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// V_DUAL_FMAC and V_DUAL_DOT2ACC_F32_F16 and V_DUAL_DOT2ACC_F32_BF16 need a
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// dummy src2 tied to dst for passes to track its uses. Its presence does not
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// affect VOPD formation rules because the rules for src2 and dst are the
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// same. src2X and src2Y should not be encoded.
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bit hasSrc2AccX = !or(!eq(VDX.Mnemonic, "v_fmac_f32"), !eq(VDX.Mnemonic, "v_dot2c_f32_f16"), !eq(VDX.Mnemonic, "v_dot2c_f32_bf16"));
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bit hasSrc2AccY = !or(!eq(VDY.Mnemonic, "v_fmac_f32"), !eq(VDY.Mnemonic, "v_dot2c_f32_f16"), !eq(VDY.Mnemonic, "v_dot2c_f32_bf16"));
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string ConstraintsX = !if(hasSrc2AccX, "$src2X = $vdstX", "");
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string ConstraintsY = !if(hasSrc2AccY, "$src2Y = $vdstY", "");
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let Constraints =
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ConstraintsX # !if(!and(hasSrc2AccX, hasSrc2AccY), ", ", "") # ConstraintsY;
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string DisableEncodingX = !if(hasSrc2AccX, "$src2X", "");
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string DisableEncodingY = !if(hasSrc2AccY, "$src2Y", "");
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let DisableEncoding =
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DisableEncodingX # !if(!and(hasSrc2AccX, hasSrc2AccY), ", ", "") # DisableEncodingY;
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let Uses = RegListUnion<VDX.Uses, VDY.Uses>.ret;
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let Defs = RegListUnion<VDX.Defs, VDY.Defs>.ret;
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let SchedRW = !listconcat(VDX.SchedRW, VDY.SchedRW);
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}
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class VOPD<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
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VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
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: VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,
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VOPDe<XasVC.VOPDOp{3-0}, YasVC.VOPDOp{4-0}> {
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let Inst{16-9} = !if (!eq(VDX.Mnemonic, "v_mov_b32"), 0x0, vsrc1X);
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let Inst{48-41} = !if (!eq(VDY.Mnemonic, "v_mov_b32"), 0x0, vsrc1Y);
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}
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class VOPD_MADK<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
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VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
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: VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,
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VOPD_MADKe<XasVC.VOPDOp{3-0}, YasVC.VOPDOp{4-0}> {
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let Inst{16-9} = !if (!eq(VDX.Mnemonic, "v_mov_b32"), 0x0, vsrc1X);
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let Inst{48-41} = !if (!eq(VDY.Mnemonic, "v_mov_b32"), 0x0, vsrc1Y);
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let Size = 12;
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let FixedSize = 1;
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}
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class VOPD3<dag outs, dag ins, string asm, VOP_Pseudo VDX, VOP_Pseudo VDY,
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VOPD_Component XasVC, VOPD_Component YasVC, GFXGenD Gen>
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: VOPD_Base<outs, ins, asm, VDX, VDY, XasVC, YasVC, Gen>,
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VOPD3e<XasVC.VOPDOp, YasVC.VOPDOp, VDX, VDY> {
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let VOPD3 = 1;
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let Size = 12;
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// VOPD3 uses promoted form of VOP2 instructions, so V_CNDMASK_B32 is not
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// limited to VCC src2 only, and a real SGPR will be used as an operand
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// instead.
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defvar UsesX = !if(!eq(VDX, V_CNDMASK_B32_e32), !filter(x, VDX.Uses, !ne(x, VCC)), VDX.Uses);
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defvar UsesY = !if(!eq(VDY, V_CNDMASK_B32_e32), !filter(x, VDY.Uses, !ne(x, VCC)), VDY.Uses);
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let Uses = RegListUnion<UsesX, UsesY>.ret;
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}
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defvar VOPDPseudosCommon = [
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"V_FMAC_F32_e32", "V_FMAAK_F32", "V_FMAMK_F32", "V_MUL_F32_e32",
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"V_ADD_F32_e32", "V_SUB_F32_e32", "V_SUBREV_F32_e32", "V_MUL_LEGACY_F32_e32",
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"V_MOV_B32_e32", "V_CNDMASK_B32_e32", "V_MAX_F32_e32", "V_MIN_F32_e32",
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"V_DOT2C_F32_F16_e32", "V_DOT2C_F32_BF16_e32"
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];
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defvar VOPDYOnlyPseudosCommon = ["V_ADD_U32_e32", "V_LSHLREV_B32_e32"];
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defvar VOPDYOnlyPseudosGFX11_12 = ["V_AND_B32_e32"];
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defvar VOPDYOnlyPseudosGFX1250 = ["V_MAX_I32_e32", "V_MIN_I32_e32",
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"V_SUB_U32_e32", "V_LSHRREV_B32_e32",
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"V_ASHRREV_I32_e32"];
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defvar VOPDXPseudosGFX11 = VOPDPseudosCommon;
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defvar VOPDXPseudosGFX12 = VOPDPseudosCommon;
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defvar VOPDYPseudosGFX11 = !listconcat(VOPDXPseudosGFX11, VOPDYOnlyPseudosCommon, VOPDYOnlyPseudosGFX11_12);
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defvar VOPDYPseudosGFX12 = !listconcat(VOPDXPseudosGFX12, VOPDYOnlyPseudosCommon, VOPDYOnlyPseudosGFX11_12);
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defvar VOPDYPseudosGFX1250 = !listconcat(VOPDXPseudosGFX12, VOPDYOnlyPseudosCommon, VOPDYOnlyPseudosGFX1250);
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def GFX11GenD : GFXGenD<GFX11Gen, VOPDXPseudosGFX11, VOPDYPseudosGFX11>;
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def GFX12GenD : GFXGenD<GFX12Not12_50Gen, VOPDXPseudosGFX12, VOPDYPseudosGFX12>;
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def GFX1250GenD : GFXGenD<GFX1250Gen, VOPDXPseudosGFX12, VOPDYPseudosGFX1250>;
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def VOPDDstYOperand : RegisterOperand<VGPR_32, "printRegularOperand"> {
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let DecoderMethod = "decodeOperandVOPDDstY";
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}
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class getRenamed<string VOPDName, GFXGen Gen> {
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string ret = !cond(!eq(Gen.Subtarget, GFX11Gen.Subtarget) : VOPDName,
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!eq(VOPDName, "v_dual_max_f32") : "v_dual_max_num_f32",
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!eq(VOPDName, "v_dual_min_f32") : "v_dual_min_num_f32",
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true : VOPDName);
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}
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foreach Gen = [GFX11GenD, GFX12GenD, GFX1250GenD] in {
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foreach x = Gen.VOPDXPseudos in {
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foreach y = Gen.VOPDYPseudos in {
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defvar xInst = !cast<VOP_Pseudo>(x);
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defvar yInst = !cast<VOP_Pseudo>(y);
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defvar XasVC = !cast<VOPD_Component>(x);
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defvar YasVC = !cast<VOPD_Component>(y);
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defvar xAsmName = getRenamed<XasVC.VOPDName, Gen>.ret;
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defvar yAsmName = getRenamed<YasVC.VOPDName, Gen>.ret;
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defvar isMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"),
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!eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));
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defvar isOpXMADK = !or(!eq(x, "V_FMAAK_F32"), !eq(x, "V_FMAMK_F32"));
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defvar isOpYMADK = !or(!eq(y, "V_FMAAK_F32"), !eq(y, "V_FMAMK_F32"));
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defvar OpName = "V_DUAL_" # !substr(x,2) # "_X_" # !substr(y,2) # Gen.Suffix;
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defvar outs = (outs VGPRSrc_32:$vdstX, VOPDDstYOperand:$vdstY);
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if !or(isOpXMADK, isOpYMADK) then {
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// If Both X and Y are MADK, the mandatory literal of X additionally must
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// use an alternate operand format which defers to the 'real' Y literal.
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defvar isOpXYMADK = !and(isOpXMADK, isOpYMADK);
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defvar X_MADK_Pfl = !cast<VOP_MADK_Base>(xInst.Pfl);
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defvar asm = xAsmName #" "#
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!if(isOpXYMADK, X_MADK_Pfl.AsmVOPDX_immX, xInst.Pfl.AsmVOPDX)#
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" :: "# yAsmName #" "# yInst.Pfl.AsmVOPDY;
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defvar ins = !con(!if(isOpXYMADK, xInst.Pfl.InsVOPDX_immX, xInst.Pfl.InsVOPDX),
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yInst.Pfl.InsVOPDY);
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def OpName : VOPD_MADK<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;
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} else {
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defvar ins = !con(xInst.Pfl.InsVOPDX, yInst.Pfl.InsVOPDY);
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defvar asm = xAsmName #" "# xInst.Pfl.AsmVOPDX #" :: "# yAsmName #" "# yInst.Pfl.AsmVOPDY;
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def OpName : VOPD<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;
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}
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}
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}
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}
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defvar VOPD3XPseudosExtra = ["V_ADD_U32_e32", "V_LSHLREV_B32_e32", "V_FMA_F32_e64", "V_SUB_U32_e32",
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"V_LSHRREV_B32_e32", "V_ASHRREV_I32_e32", "V_FMA_F64_e64", "V_ADD_F64_pseudo_e32",
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"V_MUL_F64_pseudo_e32", "V_MAX_NUM_F64_e32", "V_MIN_NUM_F64_e32"];
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defvar VOPD3XPseudosGFX1250 = !listconcat(
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!filter(x, VOPDXPseudosGFX12, !and(!eq(!find(x, "FMAAK"), -1),
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!eq(!find(x, "FMAMK"), -1))),
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VOPD3XPseudosExtra);
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defvar VOPD3YPseudosExtra = ["V_BITOP3_B32_e64", "V_FMA_F32_e64"];
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defvar VOPD3YPseudosGFX1250 = !listconcat(
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!filter(x, VOPDYPseudosGFX1250, !and(!eq(!find(x, "FMAAK"), -1),
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!eq(!find(x, "FMAMK"), -1))),
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VOPD3YPseudosExtra);
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def GFX1250GenD3 : GFXGenD<GFX1250Gen, VOPD3XPseudosGFX1250, VOPD3YPseudosGFX1250>;
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class getOpcMap<string OPName> {
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defvar BaseName = !substr(OPName,2);
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string ret = !cond(!eq(BaseName, "BITOP3_B32_e64") : "BITOP2_B32_e64",
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1 : BaseName);
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}
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foreach Gen = [GFX1250GenD3] in {
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foreach x = Gen.VOPDXPseudos in {
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foreach y = Gen.VOPDYPseudos in {
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defvar xInst = !cast<VOP_Pseudo>(x);
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defvar yInst = !cast<VOP_Pseudo>(y);
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defvar XasVC = !cast<VOPD_Component>(x);
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defvar YasVC = !cast<VOPD_Component>(y);
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defvar xAsmName = getRenamed<XasVC.VOPDName, Gen>.ret;
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defvar yAsmName = getRenamed<YasVC.VOPDName, Gen>.ret;
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defvar OpName = "V_DUAL_" # getOpcMap<x>.ret # "_X_" # getOpcMap<y>.ret # "_e96" # Gen.Suffix;
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defvar asm = xAsmName # xInst.Pfl.AsmVOPD3X #" :: "# yAsmName #" "# yInst.Pfl.AsmVOPD3Y;
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defvar ins = !con(xInst.Pfl.InsVOPD3X, yInst.Pfl.InsVOPD3Y);
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defvar outs = (outs xInst.Pfl.DstRC:$vdstX, yInst.Pfl.DstRC:$vdstY);
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def OpName : VOPD3<outs, ins, asm, xInst, yInst, XasVC, YasVC, Gen>;
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}
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}
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}
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