4cce10743d
Had been doing this piece by piece, but makes more sense to do it in a single PR. Adds support for `ARID`, `PCI`, `PCD`, `AL`, and `ARD` addressing modes for atomic operations, along with a variety of tests. The `CodeModel` tests have been rearranged, as some of the new addressing modes are only exercised under some combinations of `CodeModel` and relocation mode
126 lines
5.8 KiB
TableGen
126 lines
5.8 KiB
TableGen
//===-- M68kInstrAtomics.td - Atomics Instructions ---------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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foreach size = [8, 16, 32] in {
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def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARI:$ptr),
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(!cast<MxInst>("MOV"#size#"dj") !cast<MxMemOp>("MxARI"#size):$ptr)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARII:$ptr),
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(!cast<MxInst>("MOV"#size#"df") !cast<MxMemOp>("MxARII"#size):$ptr)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_ARID:$ptr),
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(!cast<MxInst>("MOV"#size#"dp") !cast<MxMemOp>("MxARID"#size):$ptr)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_PCD:$ptr),
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(!cast<MxInst>("MOV"#size#"dq") !cast<MxMemOp>("MxPCD"#size):$ptr)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_load_"#size) MxCP_PCI:$ptr),
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(!cast<MxInst>("MOV"#size#"dk") !cast<MxMemOp>("MxPCI"#size):$ptr)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARI:$ptr),
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(!cast<MxInst>("MOV"#size#"jd") !cast<MxMemOp>("MxARI"#size):$ptr,
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!cast<MxRegOp>("MxDRD"#size):$val)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARII:$ptr),
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(!cast<MxInst>("MOV"#size#"fd") !cast<MxMemOp>("MxARII"#size):$ptr,
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!cast<MxRegOp>("MxDRD"#size):$val)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_ARID:$ptr),
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(!cast<MxInst>("MOV"#size#"pd") !cast<MxMemOp>("MxARID"#size):$ptr,
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!cast<MxRegOp>("MxDRD"#size):$val)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_PCD:$ptr),
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(!cast<MxInst>("MOV"#size#"qd") !cast<MxMemOp>("MxPCD"#size):$ptr,
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!cast<MxRegOp>("MxDRD"#size):$val)>;
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def : Pat<(!cast<SDPatternOperator>("atomic_store_"#size) !cast<MxRegOp>("MxDRD"#size):$val, MxCP_PCI:$ptr),
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(!cast<MxInst>("MOV"#size#"kd") !cast<MxMemOp>("MxPCI"#size):$ptr,
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!cast<MxRegOp>("MxDRD"#size):$val)>;
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}
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let Predicates = [AtLeastM68020] in {
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class MxCASARIOp<bits<2> size_encoding, MxType type>
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: MxInst<(outs type.ROp:$out),
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(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARI"#type.Size):$mem),
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"cas."#type.Prefix#" $dc, $du, $mem"> {
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let Inst = (ascend
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(descend 0b00001, size_encoding, 0b011, MxEncAddrMode_j<"mem">.EA),
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(descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
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);
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let Constraints = "$out = $dc";
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let mayLoad = 1;
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let mayStore = 1;
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}
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def CASARI8 : MxCASARIOp<0x1, MxType8d>;
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def CASARI16 : MxCASARIOp<0x2, MxType16d>;
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def CASARI32 : MxCASARIOp<0x3, MxType32d>;
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class MxCASARIDOp<bits<2> size_encoding, MxType type>
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: MxInst<(outs type.ROp:$out),
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(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARID"#type.Size):$mem),
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"cas."#type.Prefix#" $dc, $du, $mem"> {
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let Inst = (ascend
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(descend 0b00001, size_encoding, 0b011, MxEncAddrMode_p<"mem">.EA),
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(descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
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);
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let Constraints = "$out = $dc";
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let mayLoad = 1;
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let mayStore = 1;
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}
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def CASARID8 : MxCASARIDOp<0x1, MxType8d>;
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def CASARID16 : MxCASARIDOp<0x2, MxType16d>;
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def CASARID32 : MxCASARIDOp<0x3, MxType32d>;
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class MxCASARIIOp<bits<2> size_encoding, MxType type>
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: MxInst<(outs type.ROp:$out),
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(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxARII"#type.Size):$mem),
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"cas."#type.Prefix#" $dc, $du, $mem"> {
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let Inst = (ascend
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(descend 0b00001, size_encoding, 0b011, MxEncAddrMode_f<"mem">.EA),
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(descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
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);
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let Constraints = "$out = $dc";
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let mayLoad = 1;
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let mayStore = 1;
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}
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def CASARII8 : MxCASARIIOp<0x1, MxType8d>;
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def CASARII16 : MxCASARIIOp<0x2, MxType16d>;
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def CASARII32 : MxCASARIIOp<0x3, MxType32d>;
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class MxCASALOp<bits<2> size_encoding, MxType type>
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: MxInst<(outs type.ROp:$out),
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(ins type.ROp:$dc, type.ROp:$du, !cast<MxMemOp>("MxAL"#type.Size):$mem),
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"cas."#type.Prefix#" $dc, $du, $mem"> {
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let Inst = (ascend
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(descend 0b00001, size_encoding, 0b011, MxEncAddrMode_abs<"mem">.EA),
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(descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
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);
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let Constraints = "$out = $dc";
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let mayLoad = 1;
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let mayStore = 1;
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}
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def CASAL8 : MxCASALOp<0x1, MxType8d>;
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def CASAL16 : MxCASALOp<0x2, MxType16d>;
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def CASAL32 : MxCASALOp<0x3, MxType32d>;
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foreach mode = ["ARI", "ARII", "ARID", "AL"] in {
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foreach size = [8, 16, 32] in {
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def : Pat<(!cast<SDPatternOperator>("atomic_cmp_swap_i"#size) !cast<ComplexPattern>("MxCP_"#mode):$ptr,
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!cast<MxRegOp>("MxDRD"#size):$cmp,
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!cast<MxRegOp>("MxDRD"#size):$new),
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(!cast<MxInst>("CAS"#mode#size) !cast<MxRegOp>("MxDRD"#size):$cmp,
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!cast<MxRegOp>("MxDRD"#size):$new,
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!cast<MxMemOp>("Mx"#mode#size):$ptr)>;
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} // size
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} // addr mode
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} // let Predicates = [AtLeastM68020]
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