c7500a2ec3
Instead of creating two separate fixups, create a single one. Leverage RISCVAsmBackend::addReloc to generate ADD/SUB relocation pairs. In a future change MCFragment::setVarFixup may be restricted to a single fixup.
74 lines
2.8 KiB
C++
74 lines
2.8 KiB
C++
//===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries -------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVFIXUPKINDS_H
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/MC/MCFixup.h"
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#include <utility>
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#undef RISCV
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namespace llvm::RISCV {
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enum Fixups {
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// 20-bit fixup corresponding to %hi(foo) for instructions like lui
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fixup_riscv_hi20 = FirstTargetFixupKind,
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// 12-bit fixup corresponding to %lo(foo) for instructions like addi
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fixup_riscv_lo12_i,
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// 12-bit fixup corresponding to foo-bar for instructions like addi
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fixup_riscv_12_i,
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// 12-bit fixup corresponding to %lo(foo) for the S-type store instructions
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fixup_riscv_lo12_s,
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// 20-bit fixup corresponding to %pcrel_hi(foo) for instructions like auipc
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fixup_riscv_pcrel_hi20,
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// 12-bit fixup corresponding to %pcrel_lo(foo) for instructions like addi
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fixup_riscv_pcrel_lo12_i,
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// 12-bit fixup corresponding to %pcrel_lo(foo) for the S-type store
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// instructions
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fixup_riscv_pcrel_lo12_s,
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// 20-bit fixup for symbol references in the jal instruction
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fixup_riscv_jal,
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// 12-bit fixup for symbol references in the branch instructions
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fixup_riscv_branch,
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// 11-bit fixup for symbol references in the compressed jump instruction
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fixup_riscv_rvc_jump,
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// 8-bit fixup for symbol references in the compressed branch instruction
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fixup_riscv_rvc_branch,
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// 6-bit fixup for symbol references in instructions like c.li
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fixup_riscv_rvc_imm,
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// Fixup representing a legacy no-pic function call attached to the auipc
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// instruction in a pair composed of adjacent auipc+jalr instructions.
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fixup_riscv_call,
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// Fixup representing a function call attached to the auipc instruction in a
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// pair composed of adjacent auipc+jalr instructions.
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fixup_riscv_call_plt,
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// Qualcomm specific fixups
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// 12-bit fixup for symbol references in the 48-bit Xqcibi branch immediate
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// instructions
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fixup_riscv_qc_e_branch,
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// 32-bit fixup for symbol references in the 48-bit qc.e.li instruction
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fixup_riscv_qc_e_32,
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// 20-bit fixup for symbol references in the 32-bit qc.li instruction
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fixup_riscv_qc_abs20_u,
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// 32-bit fixup for symbol references in the 48-bit qc.j/qc.jal instructions
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fixup_riscv_qc_e_call_plt,
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// Andes specific fixups
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// 10-bit fixup for symbol references in the xandesperf branch instruction
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fixup_riscv_nds_branch_10,
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// Used as a sentinel, must be the last
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fixup_riscv_invalid,
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NumTargetFixupKinds = fixup_riscv_invalid - FirstTargetFixupKind
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};
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} // end namespace llvm::RISCV
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#endif
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