a0b6cfd975
This adds assembler/disassembler support for XSfmmbase 0.6 and related SiFive matrix multiplication extensions based on the spec here https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification Functionality-wise, this is the same as the Zvma extension proposal that SiFive shared with the Attached Matrix Extension Task Group. The extension names and instruction mnemonics have been changed to use vendor prefixes. Note this is a non-conforming extension as the opcodes used here are in the standard opcode space in OP-V or OP-VE. --------- Co-authored-by: Brandon Wu <brandon.wu@sifive.com>
82 lines
3.8 KiB
C++
82 lines
3.8 KiB
C++
//===-- RISCVInstPrinter.h - Convert RISC-V MCInst to asm syntax --*- C++ -*--//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints a RISC-V MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVINSTPRINTER_H
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#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVINSTPRINTER_H
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/MC/MCInstPrinter.h"
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namespace llvm {
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class RISCVInstPrinter : public MCInstPrinter {
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public:
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RISCVInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI)
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: MCInstPrinter(MAI, MII, MRI) {}
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bool applyTargetSpecificCLOption(StringRef Opt) override;
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void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
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const MCSubtargetInfo &STI, raw_ostream &O) override;
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void printRegName(raw_ostream &O, MCRegister Reg) override;
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void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printBranchOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printFenceArg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printFRMArgLegacy(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printFPImmOperand(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printXSfmmVType(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printVMaskReg(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printRegList(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printStackAdj(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O,
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bool Negate = false);
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void printNegStackAdj(const MCInst *MI, unsigned OpNo,
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const MCSubtargetInfo &STI, raw_ostream &O) {
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return printStackAdj(MI, OpNo, STI, O, /*Negate*/ true);
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}
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void printRegReg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &O);
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// Autogenerated by tblgen.
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std::pair<const char *, uint64_t>
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getMnemonic(const MCInst &MI) const override;
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void printInstruction(const MCInst *MI, uint64_t Address,
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const MCSubtargetInfo &STI, raw_ostream &O);
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bool printAliasInstr(const MCInst *MI, uint64_t Address,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printCustomAliasOperand(const MCInst *MI, uint64_t Address,
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unsigned OpIdx, unsigned PrintMethodIdx,
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const MCSubtargetInfo &STI, raw_ostream &O);
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static const char *getRegisterName(MCRegister Reg);
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static const char *getRegisterName(MCRegister Reg, unsigned AltIdx);
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};
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} // namespace llvm
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#endif
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