a6eb5eee38
As of 20b5728b7b1ccc4509a316efb270d46cc9526d69, C always enables Zca, so the check `C || Zca` is equivalent to just checking for `Zca`. This replaces any uses of `HasStdExtCOrZca` with a new `HasStdExtZca` (with the same assembler description, to avoid changes in error messages), and simplifies everywhere where C++ needed to check for either C or Zca. The Subtarget function is just deprecated for the moment.
587 lines
21 KiB
C++
587 lines
21 KiB
C++
//===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVMatInt.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
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if (!HasRVC)
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return Res.size();
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int Cost = 0;
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for (auto Instr : Res) {
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// Assume instructions that aren't listed aren't compressible.
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bool Compressed = false;
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switch (Instr.getOpcode()) {
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case RISCV::QC_E_LI:
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// One 48-bit instruction takes the space of 1.5 regular instructions.
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Cost += 150;
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continue;
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case RISCV::SLLI:
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case RISCV::SRLI:
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Compressed = true;
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break;
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case RISCV::ADDI:
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case RISCV::ADDIW:
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case RISCV::LUI:
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Compressed = isInt<6>(Instr.getImm());
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break;
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}
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// Two RVC instructions take the same space as one RVI instruction, but
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// can take longer to execute than the single RVI instruction. Thus, we
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// consider that two RVC instruction are slightly more costly than one
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// RVI instruction. For longer sequences of RVC instructions the space
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// savings can be worth it, though. The costs below try to model that.
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if (!Compressed)
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Cost += 100; // Baseline cost of one RVI instruction: 100%.
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else
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Cost += 70; // 70% cost of baseline.
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}
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return Cost;
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}
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// Recursively generate a sequence for materializing an integer.
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static void generateInstSeqImpl(int64_t Val, const MCSubtargetInfo &STI,
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RISCVMatInt::InstSeq &Res) {
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bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
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// Use BSETI for a single bit that can't be expressed by a single LUI or ADDI.
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if (STI.hasFeature(RISCV::FeatureStdExtZbs) && isPowerOf2_64(Val) &&
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(!isInt<32>(Val) || Val == 0x800)) {
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Res.emplace_back(RISCV::BSETI, Log2_64(Val));
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return;
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}
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if (!IsRV64 && STI.hasFeature(RISCV::FeatureVendorXqcili)) {
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bool FitsOneStandardInst = ((Val & 0xFFF) == 0) || isInt<12>(Val);
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// 20-bit signed immediates that don't fit into `ADDI` or `LUI` should use
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// `QC.LI` (a single 32-bit instruction).
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if (!FitsOneStandardInst && isInt<20>(Val)) {
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Res.emplace_back(RISCV::QC_LI, Val);
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return;
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}
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// 32-bit signed immediates that don't fit into `ADDI`, `LUI` or `QC.LI`
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// should use `QC.E.LI` (a single 48-bit instruction).
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if (!FitsOneStandardInst && isInt<32>(Val)) {
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Res.emplace_back(RISCV::QC_E_LI, Val);
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return;
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}
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}
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if (isInt<32>(Val)) {
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// Depending on the active bits in the immediate Value v, the following
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// instruction sequences are emitted:
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//
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// v == 0 : ADDI
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// v[0,12) != 0 && v[12,32) == 0 : ADDI
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// v[0,12) == 0 && v[12,32) != 0 : LUI
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// v[0,32) != 0 : LUI+ADDI(W)
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int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
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int64_t Lo12 = SignExtend64<12>(Val);
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if (Hi20)
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Res.emplace_back(RISCV::LUI, Hi20);
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if (Lo12 || Hi20 == 0) {
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unsigned AddiOpc = RISCV::ADDI;
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if (IsRV64 && Hi20) {
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// Use ADDIW rather than ADDI only when necessary for correctness. As
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// noted in RISCVOptWInstrs, this helps reduce test differences vs
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// RV32 without being a pessimization.
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int64_t LuiRes = SignExtend64<32>(Hi20 << 12);
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if (!isInt<32>(LuiRes + Lo12))
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AddiOpc = RISCV::ADDIW;
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}
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Res.emplace_back(AddiOpc, Lo12);
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}
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return;
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}
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assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
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// In the worst case, for a full 64-bit constant, a sequence of 8 instructions
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// (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emitted. Note
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// that the first two instructions (LUI+ADDIW) can contribute up to 32 bits
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// while the following ADDI instructions contribute up to 12 bits each.
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//
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// On the first glance, implementing this seems to be possible by simply
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// emitting the most significant 32 bits (LUI+ADDIW) followed by as many left
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// shift (SLLI) and immediate additions (ADDI) as needed. However, due to the
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// fact that ADDI performs a sign extended addition, doing it like that would
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// only be possible when at most 11 bits of the ADDI instructions are used.
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// Using all 12 bits of the ADDI instructions, like done by GAS, actually
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// requires that the constant is processed starting with the least significant
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// bit.
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//
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// In the following, constants are processed from LSB to MSB but instruction
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// emission is performed from MSB to LSB by recursively calling
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// generateInstSeq. In each recursion, first the lowest 12 bits are removed
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// from the constant and the optimal shift amount, which can be greater than
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// 12 bits if the constant is sparse, is determined. Then, the shifted
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// remaining constant is processed recursively and gets emitted as soon as it
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// fits into 32 bits. The emission of the shifts and additions is subsequently
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// performed when the recursion returns.
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int64_t Lo12 = SignExtend64<12>(Val);
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Val = (uint64_t)Val - (uint64_t)Lo12;
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int ShiftAmount = 0;
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bool Unsigned = false;
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// Val might now be valid for LUI without needing a shift.
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if (!isInt<32>(Val)) {
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ShiftAmount = llvm::countr_zero((uint64_t)Val);
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Val >>= ShiftAmount;
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// If the remaining bits don't fit in 12 bits, we might be able to reduce
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// the // shift amount in order to use LUI which will zero the lower 12
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// bits.
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if (ShiftAmount > 12 && !isInt<12>(Val)) {
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if (isInt<32>((uint64_t)Val << 12)) {
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// Reduce the shift amount and add zeros to the LSBs so it will match
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// LUI.
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ShiftAmount -= 12;
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Val = (uint64_t)Val << 12;
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} else if (isUInt<32>((uint64_t)Val << 12) &&
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STI.hasFeature(RISCV::FeatureStdExtZba)) {
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// Reduce the shift amount and add zeros to the LSBs so it will match
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// LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
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ShiftAmount -= 12;
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Val = ((uint64_t)Val << 12) | (0xffffffffull << 32);
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Unsigned = true;
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}
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}
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// Try to use SLLI_UW for Val when it is uint32 but not int32.
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if (isUInt<32>(Val) && !isInt<32>(Val) &&
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STI.hasFeature(RISCV::FeatureStdExtZba)) {
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// Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with
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// SLLI_UW.
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Val = ((uint64_t)Val) | (0xffffffffull << 32);
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Unsigned = true;
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}
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}
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generateInstSeqImpl(Val, STI, Res);
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// Skip shift if we were able to use LUI directly.
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if (ShiftAmount) {
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unsigned Opc = Unsigned ? RISCV::SLLI_UW : RISCV::SLLI;
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Res.emplace_back(Opc, ShiftAmount);
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}
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if (Lo12)
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Res.emplace_back(RISCV::ADDI, Lo12);
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}
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static unsigned extractRotateInfo(int64_t Val) {
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// for case: 0b111..1..xxxxxx1..1..
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unsigned LeadingOnes = llvm::countl_one((uint64_t)Val);
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unsigned TrailingOnes = llvm::countr_one((uint64_t)Val);
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if (TrailingOnes > 0 && TrailingOnes < 64 &&
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(LeadingOnes + TrailingOnes) > (64 - 12))
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return 64 - TrailingOnes;
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// for case: 0bxxx1..1..1...xxx
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unsigned UpperTrailingOnes = llvm::countr_one(Hi_32(Val));
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unsigned LowerLeadingOnes = llvm::countl_one(Lo_32(Val));
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if (UpperTrailingOnes < 32 &&
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(UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
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return 32 - UpperTrailingOnes;
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return 0;
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}
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static void generateInstSeqLeadingZeros(int64_t Val, const MCSubtargetInfo &STI,
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RISCVMatInt::InstSeq &Res) {
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assert(Val > 0 && "Expected positive val");
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unsigned LeadingZeros = llvm::countl_zero((uint64_t)Val);
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uint64_t ShiftedVal = (uint64_t)Val << LeadingZeros;
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// Fill in the bits that will be shifted out with 1s. An example where this
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// helps is trailing one masks with 32 or more ones. This will generate
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// ADDI -1 and an SRLI.
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ShiftedVal |= maskTrailingOnes<uint64_t>(LeadingZeros);
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
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// Keep the new sequence if it is an improvement or the original is empty.
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if ((TmpSeq.size() + 1) < Res.size() ||
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(Res.empty() && TmpSeq.size() < 8)) {
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TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
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Res = TmpSeq;
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}
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// Some cases can benefit from filling the lower bits with zeros instead.
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ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
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TmpSeq.clear();
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generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
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// Keep the new sequence if it is an improvement or the original is empty.
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if ((TmpSeq.size() + 1) < Res.size() ||
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(Res.empty() && TmpSeq.size() < 8)) {
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TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
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Res = TmpSeq;
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}
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// If we have exactly 32 leading zeros and Zba, we can try using zext.w at
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// the end of the sequence.
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if (LeadingZeros == 32 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
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// Try replacing upper bits with 1.
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uint64_t LeadingOnesVal = Val | maskLeadingOnes<uint64_t>(LeadingZeros);
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TmpSeq.clear();
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generateInstSeqImpl(LeadingOnesVal, STI, TmpSeq);
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// Keep the new sequence if it is an improvement.
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if ((TmpSeq.size() + 1) < Res.size() ||
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(Res.empty() && TmpSeq.size() < 8)) {
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TmpSeq.emplace_back(RISCV::ADD_UW, 0);
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Res = TmpSeq;
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}
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}
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}
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namespace llvm::RISCVMatInt {
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InstSeq generateInstSeq(int64_t Val, const MCSubtargetInfo &STI) {
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RISCVMatInt::InstSeq Res;
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generateInstSeqImpl(Val, STI, Res);
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// If the low 12 bits are non-zero, the first expansion may end with an ADDI
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// or ADDIW. If there are trailing zeros, try generating a sign extended
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// constant with no trailing zeros and use a final SLLI to restore them.
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if ((Val & 0xfff) != 0 && (Val & 1) == 0 && Res.size() >= 2) {
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unsigned TrailingZeros = llvm::countr_zero((uint64_t)Val);
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int64_t ShiftedVal = Val >> TrailingZeros;
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// If we can use C.LI+C.SLLI instead of LUI+ADDI(W) prefer that since
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// its more compressible. But only if LUI+ADDI(W) isn't fusable.
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// NOTE: We don't check for C extension to minimize differences in generated
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// code.
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bool IsShiftedCompressible =
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isInt<6>(ShiftedVal) && !STI.hasFeature(RISCV::TuneLUIADDIFusion);
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(ShiftedVal, STI, TmpSeq);
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// Keep the new sequence if it is an improvement.
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if ((TmpSeq.size() + 1) < Res.size() || IsShiftedCompressible) {
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TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros);
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Res = TmpSeq;
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}
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}
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// If we have a 1 or 2 instruction sequence this is the best we can do. This
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// will always be true for RV32 and will often be true for RV64.
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if (Res.size() <= 2)
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return Res;
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assert(STI.hasFeature(RISCV::Feature64Bit) &&
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"Expected RV32 to only need 2 instructions");
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// If the lower 13 bits are something like 0x17ff, try to add 1 to change the
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// lower 13 bits to 0x1800. We can restore this with an ADDI of -1 at the end
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// of the sequence. Call generateInstSeqImpl on the new constant which may
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// subtract 0xfffffffffffff800 to create another ADDI. This will leave a
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// constant with more than 12 trailing zeros for the next recursive step.
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if ((Val & 0xfff) != 0 && (Val & 0x1800) == 0x1000) {
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int64_t Imm12 = -(0x800 - (Val & 0xfff));
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int64_t AdjustedVal = Val - Imm12;
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(AdjustedVal, STI, TmpSeq);
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// Keep the new sequence if it is an improvement.
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if ((TmpSeq.size() + 1) < Res.size()) {
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TmpSeq.emplace_back(RISCV::ADDI, Imm12);
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Res = TmpSeq;
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}
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}
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// If the constant is positive we might be able to generate a shifted constant
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// with no leading zeros and use a final SRLI to restore them.
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if (Val > 0 && Res.size() > 2) {
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generateInstSeqLeadingZeros(Val, STI, Res);
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}
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// If the constant is negative, trying inverting and using our trailing zero
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// optimizations. Use an xori to invert the final value.
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if (Val < 0 && Res.size() > 3) {
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uint64_t InvertedVal = ~(uint64_t)Val;
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqLeadingZeros(InvertedVal, STI, TmpSeq);
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// Keep it if we found a sequence that is smaller after inverting.
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if (!TmpSeq.empty() && (TmpSeq.size() + 1) < Res.size()) {
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TmpSeq.emplace_back(RISCV::XORI, -1);
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Res = TmpSeq;
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}
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}
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// If the Low and High halves are the same, use pack. The pack instruction
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// packs the XLEN/2-bit lower halves of rs1 and rs2 into rd, with rs1 in the
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// lower half and rs2 in the upper half.
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if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbkb)) {
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int64_t LoVal = SignExtend64<32>(Val);
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int64_t HiVal = SignExtend64<32>(Val >> 32);
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if (LoVal == HiVal) {
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(LoVal, STI, TmpSeq);
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if ((TmpSeq.size() + 1) < Res.size()) {
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TmpSeq.emplace_back(RISCV::PACK, 0);
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Res = TmpSeq;
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}
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}
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}
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// Perform optimization with BSETI in the Zbs extension.
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if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) {
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// Create a simm32 value for LUI+ADDIW by forcing the upper 33 bits to zero.
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// Xor that with original value to get which bits should be set by BSETI.
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uint64_t Lo = Val & 0x7fffffff;
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uint64_t Hi = Val ^ Lo;
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assert(Hi != 0);
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RISCVMatInt::InstSeq TmpSeq;
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if (Lo != 0)
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generateInstSeqImpl(Lo, STI, TmpSeq);
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if (TmpSeq.size() + llvm::popcount(Hi) < Res.size()) {
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do {
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TmpSeq.emplace_back(RISCV::BSETI, llvm::countr_zero(Hi));
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Hi &= (Hi - 1); // Clear lowest set bit.
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} while (Hi != 0);
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Res = TmpSeq;
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}
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// Fold LI 1 + SLLI into BSETI.
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if (Res[0].getOpcode() == RISCV::ADDI && Res[0].getImm() == 1 &&
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Res[1].getOpcode() == RISCV::SLLI) {
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Res.erase(Res.begin()); // Remove ADDI.
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Res.front() = Inst(RISCV::BSETI, Res.front().getImm()); // Patch SLLI.
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}
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}
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// Perform optimization with BCLRI in the Zbs extension.
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if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZbs)) {
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// Create a simm32 value for LUI+ADDIW by forcing the upper 33 bits to one.
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// Xor that with original value to get which bits should be cleared by
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// BCLRI.
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uint64_t Lo = Val | 0xffffffff80000000;
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uint64_t Hi = Val ^ Lo;
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assert(Hi != 0);
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RISCVMatInt::InstSeq TmpSeq;
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generateInstSeqImpl(Lo, STI, TmpSeq);
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if (TmpSeq.size() + llvm::popcount(Hi) < Res.size()) {
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do {
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TmpSeq.emplace_back(RISCV::BCLRI, llvm::countr_zero(Hi));
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Hi &= (Hi - 1); // Clear lowest set bit.
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} while (Hi != 0);
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Res = TmpSeq;
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}
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}
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// Perform optimization with SH*ADD in the Zba extension.
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if (Res.size() > 2 && STI.hasFeature(RISCV::FeatureStdExtZba)) {
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int64_t Div = 0;
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unsigned Opc = 0;
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RISCVMatInt::InstSeq TmpSeq;
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// Select the opcode and divisor.
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if ((Val % 3) == 0 && isInt<32>(Val / 3)) {
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Div = 3;
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Opc = RISCV::SH1ADD;
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} else if ((Val % 5) == 0 && isInt<32>(Val / 5)) {
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Div = 5;
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Opc = RISCV::SH2ADD;
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} else if ((Val % 9) == 0 && isInt<32>(Val / 9)) {
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Div = 9;
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Opc = RISCV::SH3ADD;
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}
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// Build the new instruction sequence.
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if (Div > 0) {
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generateInstSeqImpl(Val / Div, STI, TmpSeq);
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if ((TmpSeq.size() + 1) < Res.size()) {
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TmpSeq.emplace_back(Opc, 0);
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Res = TmpSeq;
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}
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} else {
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// Try to use LUI+SH*ADD+ADDI.
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int64_t Hi52 = ((uint64_t)Val + 0x800ull) & ~0xfffull;
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int64_t Lo12 = SignExtend64<12>(Val);
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Div = 0;
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if (isInt<32>(Hi52 / 3) && (Hi52 % 3) == 0) {
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Div = 3;
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Opc = RISCV::SH1ADD;
|
|
} else if (isInt<32>(Hi52 / 5) && (Hi52 % 5) == 0) {
|
|
Div = 5;
|
|
Opc = RISCV::SH2ADD;
|
|
} else if (isInt<32>(Hi52 / 9) && (Hi52 % 9) == 0) {
|
|
Div = 9;
|
|
Opc = RISCV::SH3ADD;
|
|
}
|
|
// Build the new instruction sequence.
|
|
if (Div > 0) {
|
|
// For Val that has zero Lo12 (implies Val equals to Hi52) should has
|
|
// already been processed to LUI+SH*ADD by previous optimization.
|
|
assert(Lo12 != 0 &&
|
|
"unexpected instruction sequence for immediate materialisation");
|
|
assert(TmpSeq.empty() && "Expected empty TmpSeq");
|
|
generateInstSeqImpl(Hi52 / Div, STI, TmpSeq);
|
|
if ((TmpSeq.size() + 2) < Res.size()) {
|
|
TmpSeq.emplace_back(Opc, 0);
|
|
TmpSeq.emplace_back(RISCV::ADDI, Lo12);
|
|
Res = TmpSeq;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Perform optimization with rori in the Zbb and th.srri in the XTheadBb
|
|
// extension.
|
|
if (Res.size() > 2 && (STI.hasFeature(RISCV::FeatureStdExtZbb) ||
|
|
STI.hasFeature(RISCV::FeatureVendorXTHeadBb))) {
|
|
if (unsigned Rotate = extractRotateInfo(Val)) {
|
|
RISCVMatInt::InstSeq TmpSeq;
|
|
uint64_t NegImm12 = llvm::rotl<uint64_t>(Val, Rotate);
|
|
assert(isInt<12>(NegImm12));
|
|
TmpSeq.emplace_back(RISCV::ADDI, NegImm12);
|
|
TmpSeq.emplace_back(STI.hasFeature(RISCV::FeatureStdExtZbb)
|
|
? RISCV::RORI
|
|
: RISCV::TH_SRRI,
|
|
Rotate);
|
|
Res = TmpSeq;
|
|
}
|
|
}
|
|
return Res;
|
|
}
|
|
|
|
void generateMCInstSeq(int64_t Val, const MCSubtargetInfo &STI,
|
|
MCRegister DestReg, SmallVectorImpl<MCInst> &Insts) {
|
|
RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, STI);
|
|
|
|
MCRegister SrcReg = RISCV::X0;
|
|
for (RISCVMatInt::Inst &Inst : Seq) {
|
|
switch (Inst.getOpndKind()) {
|
|
case RISCVMatInt::Imm:
|
|
Insts.push_back(MCInstBuilder(Inst.getOpcode())
|
|
.addReg(DestReg)
|
|
.addImm(Inst.getImm()));
|
|
break;
|
|
case RISCVMatInt::RegX0:
|
|
Insts.push_back(MCInstBuilder(Inst.getOpcode())
|
|
.addReg(DestReg)
|
|
.addReg(SrcReg)
|
|
.addReg(RISCV::X0));
|
|
break;
|
|
case RISCVMatInt::RegReg:
|
|
Insts.push_back(MCInstBuilder(Inst.getOpcode())
|
|
.addReg(DestReg)
|
|
.addReg(SrcReg)
|
|
.addReg(SrcReg));
|
|
break;
|
|
case RISCVMatInt::RegImm:
|
|
Insts.push_back(MCInstBuilder(Inst.getOpcode())
|
|
.addReg(DestReg)
|
|
.addReg(SrcReg)
|
|
.addImm(Inst.getImm()));
|
|
break;
|
|
}
|
|
|
|
// Only the first instruction has X0 as its source.
|
|
SrcReg = DestReg;
|
|
}
|
|
}
|
|
|
|
InstSeq generateTwoRegInstSeq(int64_t Val, const MCSubtargetInfo &STI,
|
|
unsigned &ShiftAmt, unsigned &AddOpc) {
|
|
int64_t LoVal = SignExtend64<32>(Val);
|
|
if (LoVal == 0)
|
|
return RISCVMatInt::InstSeq();
|
|
|
|
// Subtract the LoVal to emulate the effect of the final ADD.
|
|
uint64_t Tmp = (uint64_t)Val - (uint64_t)LoVal;
|
|
assert(Tmp != 0);
|
|
|
|
// Use trailing zero counts to figure how far we need to shift LoVal to line
|
|
// up with the remaining constant.
|
|
// TODO: This algorithm assumes all non-zero bits in the low 32 bits of the
|
|
// final constant come from LoVal.
|
|
unsigned TzLo = llvm::countr_zero((uint64_t)LoVal);
|
|
unsigned TzHi = llvm::countr_zero(Tmp);
|
|
assert(TzLo < 32 && TzHi >= 32);
|
|
ShiftAmt = TzHi - TzLo;
|
|
AddOpc = RISCV::ADD;
|
|
|
|
if (Tmp == ((uint64_t)LoVal << ShiftAmt))
|
|
return RISCVMatInt::generateInstSeq(LoVal, STI);
|
|
|
|
// If we have Zba, we can use (ADD_UW X, (SLLI X, 32)).
|
|
if (STI.hasFeature(RISCV::FeatureStdExtZba) && Lo_32(Val) == Hi_32(Val)) {
|
|
ShiftAmt = 32;
|
|
AddOpc = RISCV::ADD_UW;
|
|
return RISCVMatInt::generateInstSeq(LoVal, STI);
|
|
}
|
|
|
|
return RISCVMatInt::InstSeq();
|
|
}
|
|
|
|
int getIntMatCost(const APInt &Val, unsigned Size, const MCSubtargetInfo &STI,
|
|
bool CompressionCost, bool FreeZeroes) {
|
|
bool IsRV64 = STI.hasFeature(RISCV::Feature64Bit);
|
|
bool HasRVC = CompressionCost && STI.hasFeature(RISCV::FeatureStdExtZca);
|
|
int PlatRegSize = IsRV64 ? 64 : 32;
|
|
|
|
// Split the constant into platform register sized chunks, and calculate cost
|
|
// of each chunk.
|
|
int Cost = 0;
|
|
for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
|
|
APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
|
|
if (FreeZeroes && Chunk.getSExtValue() == 0)
|
|
continue;
|
|
InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), STI);
|
|
Cost += getInstSeqCost(MatSeq, HasRVC);
|
|
}
|
|
return std::max(FreeZeroes ? 0 : 1, Cost);
|
|
}
|
|
|
|
OpndKind Inst::getOpndKind() const {
|
|
switch (Opc) {
|
|
default:
|
|
llvm_unreachable("Unexpected opcode!");
|
|
case RISCV::LUI:
|
|
case RISCV::QC_LI:
|
|
case RISCV::QC_E_LI:
|
|
return RISCVMatInt::Imm;
|
|
case RISCV::ADD_UW:
|
|
return RISCVMatInt::RegX0;
|
|
case RISCV::SH1ADD:
|
|
case RISCV::SH2ADD:
|
|
case RISCV::SH3ADD:
|
|
case RISCV::PACK:
|
|
return RISCVMatInt::RegReg;
|
|
case RISCV::ADDI:
|
|
case RISCV::ADDIW:
|
|
case RISCV::XORI:
|
|
case RISCV::SLLI:
|
|
case RISCV::SRLI:
|
|
case RISCV::SLLI_UW:
|
|
case RISCV::RORI:
|
|
case RISCV::BSETI:
|
|
case RISCV::BCLRI:
|
|
case RISCV::TH_SRRI:
|
|
return RISCVMatInt::RegImm;
|
|
}
|
|
}
|
|
|
|
} // namespace llvm::RISCVMatInt
|