113 lines
4.4 KiB
TableGen
113 lines
4.4 KiB
TableGen
//===-- RISCVInstrInfoZalasr.td ---------------------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the Zalasr (Load-Acquire
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// and Store-Release) extension
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LAQ_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
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opcodestr, "$rd, $rs1"> {
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let rs2 = 0;
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}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO,
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(outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
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opcodestr, "$rs2, $rs1"> {
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let rd = 0;
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}
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multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> {
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def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">;
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def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> {
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def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZalasr] in {
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defm LB : LAQ_r_aq_rl<0b000, "lb">;
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defm LH : LAQ_r_aq_rl<0b001, "lh">;
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defm LW : LAQ_r_aq_rl<0b010, "lw">;
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defm SB : SRL_r_aq_rl<0b000, "sb">;
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defm SH : SRL_r_aq_rl<0b001, "sh">;
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defm SW : SRL_r_aq_rl<0b010, "sw">;
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} // Predicates = [HasStdExtZalasr]
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let Predicates = [HasStdExtZalasr, IsRV64] in {
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defm LD : LAQ_r_aq_rl<0b011, "ld">;
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defm SD : SRL_r_aq_rl<0b011, "sd">;
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} // Predicates = [HasStdExtZalasr, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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class PatLAQ<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
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: Pat<(vt (OpNode (vt GPRMemZeroOffset:$rs1))), (Inst GPRMemZeroOffset:$rs1)>;
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// n.b. this switches order of arguments
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// to deal with the fact that SRL has addr, data
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// while atomic_store has data, addr
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class PatSRL<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
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: Pat<(OpNode (vt GPR:$rs2), (vt GPRMemZeroOffset:$rs1)),
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(Inst GPRMemZeroOffset:$rs1, GPR:$rs2)>;
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let Predicates = [HasStdExtZalasr] in {
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// the sequentially consistent loads use
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// .aq instead of .aqrl to match the psABI/A.7
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def : PatLAQ<acquiring_load<atomic_load_asext_8>, LB_AQ>;
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def : PatLAQ<seq_cst_load<atomic_load_asext_8>, LB_AQ>;
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def : PatLAQ<acquiring_load<atomic_load_asext_16>, LH_AQ>;
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def : PatLAQ<seq_cst_load<atomic_load_asext_16>, LH_AQ>;
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// the sequentially consistent stores use
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// .rl instead of .aqrl to match the psABI/A.7
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def : PatSRL<releasing_store<atomic_store_8>, SB_RL>;
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def : PatSRL<seq_cst_store<atomic_store_8>, SB_RL>;
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def : PatSRL<releasing_store<atomic_store_16>, SH_RL>;
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def : PatSRL<seq_cst_store<atomic_store_16>, SH_RL>;
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def : PatSRL<releasing_store<atomic_store_32>, SW_RL>;
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def : PatSRL<seq_cst_store<atomic_store_32>, SW_RL>;
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} // Predicates = [HasStdExtZalasr]
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let Predicates = [HasStdExtZalasr, IsRV32] in {
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def : PatLAQ<acquiring_load<atomic_load_nonext_32>, LW_AQ>;
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def : PatLAQ<seq_cst_load<atomic_load_nonext_32>, LW_AQ>;
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} // Predicates = [HasStdExtZalasr, IsRV64]
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let Predicates = [HasStdExtZalasr, IsRV64] in {
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def : PatLAQ<acquiring_load<atomic_load_asext_32>, LW_AQ>;
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def : PatLAQ<seq_cst_load<atomic_load_asext_32>, LW_AQ>;
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def : PatLAQ<acquiring_load<atomic_load_nonext_64>, LD_AQ>;
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def : PatLAQ<seq_cst_load<atomic_load_nonext_64>, LD_AQ>;
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def : PatSRL<releasing_store<atomic_store_64>, SD_RL>;
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def : PatSRL<seq_cst_store<atomic_store_64>, SD_RL>;
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} // Predicates = [HasStdExtZalasr, IsRV64]
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