eca616f376
The instructions in Zqvdotq is dot-product operation. So the schedule info should be VIMulAdd rather than VIALU.
62 lines
2.6 KiB
TableGen
62 lines
2.6 KiB
TableGen
//===-- RISCVInstrInfoZvqdot.td - 'Zvqdotq' instructions ---*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the standard 'Zvqdotq'
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// extension.
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// This version is still experimental as the 'Zvqdotq' extension hasn't been
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// ratified yet.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZvqdotq] in {
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def VQDOT_VV : VALUVV<0b101100, OPMVV, "vqdot.vv">;
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def VQDOT_VX : VALUVX<0b101100, OPMVX, "vqdot.vx">;
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def VQDOTU_VV : VALUVV<0b101000, OPMVV, "vqdotu.vv">;
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def VQDOTU_VX : VALUVX<0b101000, OPMVX, "vqdotu.vx">;
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def VQDOTSU_VV : VALUVV<0b101010, OPMVV, "vqdotsu.vv">;
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def VQDOTSU_VX : VALUVX<0b101010, OPMVX, "vqdotsu.vx">;
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def VQDOTUS_VX : VALUVX<0b101110, OPMVX, "vqdotus.vx">;
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} // Predicates = [HasStdExtZvqdotq]
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let HasPassthruOp = true, HasMaskOp = true in {
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def riscv_vqdot_vl : RVSDNode<"VQDOT_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_vqdotu_vl : RVSDNode<"VQDOTU_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_vqdotsu_vl : RVSDNode<"VQDOTSU_VL", SDT_RISCVIntBinOp_VL>;
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} // let HasPassthruOp = true, HasMaskOp = true
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multiclass VPseudoVQDOT_VV_VX {
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foreach m = MxSet<32>.m in {
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defm "" : VPseudoBinaryV_VV<m>,
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SchedBinary<"WriteVIMulAddV", "ReadVIMulAddV", "ReadVIMulAddV", m.MX,
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forcePassthruRead=true>;
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defm "" : VPseudoBinaryV_VX<m>,
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SchedBinary<"WriteVIMulAddX", "ReadVIMulAddV", "ReadVIMulAddX", m.MX,
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forcePassthruRead=true>;
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}
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}
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// TODO: Add pseudo and patterns for vqdotus.vx
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// TODO: Add isCommutable for VQDOT and VQDOTU
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let Predicates = [HasStdExtZvqdotq], mayLoad = 0, mayStore = 0,
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hasSideEffects = 0 in {
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defm PseudoVQDOT : VPseudoVQDOT_VV_VX;
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defm PseudoVQDOTU : VPseudoVQDOT_VV_VX;
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defm PseudoVQDOTSU : VPseudoVQDOT_VV_VX;
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}
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defvar AllE32Vectors = [VI32MF2, VI32M1, VI32M2, VI32M4, VI32M8];
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defm : VPatBinaryVL_VV_VX<riscv_vqdot_vl, "PseudoVQDOT", AllE32Vectors>;
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defm : VPatBinaryVL_VV_VX<riscv_vqdotu_vl, "PseudoVQDOTU", AllE32Vectors>;
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defm : VPatBinaryVL_VV_VX<riscv_vqdotsu_vl, "PseudoVQDOTSU", AllE32Vectors>;
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