b57df56b48
There will be more schedule definitions for vendor extentions and we need to add these `UnsupportedSchedXXX` to exsiting models every time we add new schedule definitions. The fact is that each vendor will barely implement other vendors' extensions, so we can package these definitions into one.
279 lines
9.5 KiB
TableGen
279 lines
9.5 KiB
TableGen
//===-- RISCVSchedMIPSP8700.td - MIPS RISC-V Processor -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// P8700 - a RISC-V processor by MIPS.
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// Pipelines:
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// - 2 Integer Arithmetic and Logical Units (ALU and AL2)
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// - Multiply / Divide Unit (MDU)
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// - Branch Unit (CTI)
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// - Load Store Unit (LSU)
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// - Short Floating Point Pipe (FPUS)
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// - Long Floating Point Pipe (FPUL)
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//===----------------------------------------------------------------------===//
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def MIPSP8700Model : SchedMachineModel {
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int IssueWidth = 4;
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int MicroOpBufferSize = 96;
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int LoadLatency = 4;
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int MispredictPenalty = 8;
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let CompleteModel = 0;
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}
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let SchedModel = MIPSP8700Model in {
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// Handle ALQ Pipelines.
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// It contains 1 ALU Unit only.
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def p8700ALQ : ProcResource<1> { let BufferSize = 16; }
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// Handle AGQ Pipelines.
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def p8700AGQ : ProcResource<3> { let BufferSize = 16; }
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def p8700IssueAL2 : ProcResource<1> { let Super = p8700AGQ; }
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def p8700IssueCTI : ProcResource<1> { let Super = p8700AGQ; }
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def p8700IssueLSU : ProcResource<1> { let Super = p8700AGQ; }
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def p8700WriteEitherALU : ProcResGroup<[p8700ALQ, p8700IssueAL2]>;
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// Handle Multiply Divide Pipe.
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def p8700GpDiv : ProcResource<1>;
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def p8700GpMul : ProcResource<1>;
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def : WriteRes<WriteIALU, [p8700WriteEitherALU]>;
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def : WriteRes<WriteIALU32, [p8700WriteEitherALU]>;
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def : WriteRes<WriteShiftImm, [p8700WriteEitherALU]>;
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def : WriteRes<WriteShiftImm32, [p8700WriteEitherALU]>;
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def : WriteRes<WriteShiftReg, [p8700WriteEitherALU]>;
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def : WriteRes<WriteShiftReg32, [p8700WriteEitherALU]>;
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// Handle zba.
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def : WriteRes<WriteSHXADD, [p8700WriteEitherALU]>;
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def : WriteRes<WriteSHXADD32, [p8700WriteEitherALU]>;
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// Handle zbb.
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let Latency = 2 in {
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def : WriteRes<WriteCLZ, [p8700IssueAL2]>;
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def : WriteRes<WriteCTZ, [p8700IssueAL2]>;
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def : WriteRes<WriteCPOP, [p8700IssueAL2]>;
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def : WriteRes<WriteCLZ32, [p8700IssueAL2]>;
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def : WriteRes<WriteCTZ32, [p8700IssueAL2]>;
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def : WriteRes<WriteCPOP32, [p8700IssueAL2]>;
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}
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def : WriteRes<WriteRotateReg, [p8700WriteEitherALU]>;
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def : WriteRes<WriteRotateImm, [p8700WriteEitherALU]>;
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def : WriteRes<WriteRotateReg32, [p8700WriteEitherALU]>;
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def : WriteRes<WriteRotateImm32, [p8700WriteEitherALU]>;
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def : WriteRes<WriteREV8, [p8700WriteEitherALU]>;
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def : WriteRes<WriteORCB, [p8700WriteEitherALU]>;
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def : WriteRes<WriteIMinMax, [p8700WriteEitherALU]>;
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let Latency = 0 in
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def : WriteRes<WriteNop, [p8700WriteEitherALU]>;
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let Latency = 4 in {
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def : WriteRes<WriteLDB, [p8700IssueLSU]>;
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def : WriteRes<WriteLDH, [p8700IssueLSU]>;
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def : WriteRes<WriteLDW, [p8700IssueLSU]>;
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def : WriteRes<WriteLDD, [p8700IssueLSU]>;
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def : WriteRes<WriteAtomicW, [p8700IssueLSU]>;
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def : WriteRes<WriteAtomicD, [p8700IssueLSU]>;
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def : WriteRes<WriteAtomicLDW, [p8700IssueLSU]>;
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def : WriteRes<WriteAtomicLDD, [p8700IssueLSU]>;
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}
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let Latency = 8 in {
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def : WriteRes<WriteFLD32, [p8700IssueLSU]>;
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def : WriteRes<WriteFLD64, [p8700IssueLSU]>;
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}
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let Latency = 3 in {
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def : WriteRes<WriteSTB, [p8700IssueLSU]>;
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def : WriteRes<WriteSTH, [p8700IssueLSU]>;
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def : WriteRes<WriteSTW, [p8700IssueLSU]>;
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def : WriteRes<WriteSTD, [p8700IssueLSU]>;
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def : WriteRes<WriteAtomicSTW, [p8700IssueLSU]>;
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def : WriteRes<WriteAtomicSTD, [p8700IssueLSU]>;
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}
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def : WriteRes<WriteFST32, [p8700IssueLSU]>;
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def : WriteRes<WriteFST64, [p8700IssueLSU]>;
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let Latency = 7 in {
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def : WriteRes<WriteFMovI32ToF32, [p8700IssueLSU]>;
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def : WriteRes<WriteFMovF32ToI32, [p8700IssueLSU]>;
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def : WriteRes<WriteFMovI64ToF64, [p8700IssueLSU]>;
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def : WriteRes<WriteFMovF64ToI64, [p8700IssueLSU]>;
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}
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let Latency = 4 in {
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def : WriteRes<WriteIMul, [p8700GpMul]>;
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def : WriteRes<WriteIMul32, [p8700GpMul]>;
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}
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let Latency = 7, ReleaseAtCycles = [7] in {
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def : WriteRes<WriteIDiv, [p8700GpDiv]>;
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def : WriteRes<WriteIDiv32, [p8700GpDiv]>;
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def : WriteRes<WriteIRem, [p8700GpDiv]>;
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def : WriteRes<WriteIRem32, [p8700GpDiv]>;
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}
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def : WriteRes<WriteCSR, [p8700ALQ]>;
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// Handle CTI Pipeline.
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def : WriteRes<WriteJmp, [p8700IssueCTI]>;
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def : WriteRes<WriteJal, [p8700IssueCTI]>;
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def : WriteRes<WriteJalr, [p8700IssueCTI]>;
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// Handle FPU Pipelines.
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def p8700FPQ : ProcResource<3> { let BufferSize = 16; }
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def p8700IssueFPUS : ProcResource<1> { let Super = p8700FPQ; }
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def p8700IssueFPUL : ProcResource<1> { let Super = p8700FPQ; }
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def p8700FpuApu : ProcResource<1>;
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def p8700FpuLong : ProcResource<1>;
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let Latency = 4 in {
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def : WriteRes<WriteFCvtI32ToF32, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtI32ToF64, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtI64ToF32, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtI64ToF64, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtF32ToI32, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtF32ToI64, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtF32ToF64, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtF64ToI32, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtF64ToI64, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFCvtF64ToF32, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFAdd32, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFAdd64, [p8700IssueFPUL, p8700FpuApu]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFSGNJ32, [p8700IssueFPUS, p8700FpuApu]>;
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def : WriteRes<WriteFMinMax32, [p8700IssueFPUS, p8700FpuApu]>;
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def : WriteRes<WriteFSGNJ64, [p8700IssueFPUS, p8700FpuApu]>;
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def : WriteRes<WriteFMinMax64, [p8700IssueFPUS, p8700FpuApu]>;
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def : WriteRes<WriteFCmp32, [p8700IssueFPUS, p8700FpuApu]>;
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def : WriteRes<WriteFCmp64, [p8700IssueFPUS, p8700FpuApu]>;
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}
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def : WriteRes<WriteFClass32, [p8700IssueFPUS, p8700FpuApu]>;
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def : WriteRes<WriteFClass64, [p8700IssueFPUS, p8700FpuApu]>;
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let Latency = 8 in {
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def : WriteRes<WriteFMA32, [p8700FpuLong, p8700FpuApu]>;
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def : WriteRes<WriteFMA64, [p8700FpuLong, p8700FpuApu]>;
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}
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let Latency = 5 in {
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def : WriteRes<WriteFMul32, [p8700FpuLong, p8700FpuApu]>;
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def : WriteRes<WriteFMul64, [p8700FpuLong, p8700FpuApu]>;
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}
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let Latency = 11, ReleaseAtCycles = [1, 11] in {
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def : WriteRes<WriteFDiv32, [p8700FpuLong, p8700FpuApu]>;
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def : WriteRes<WriteFSqrt32, [p8700FpuLong, p8700FpuApu]>;
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}
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let Latency = 17, ReleaseAtCycles = [1, 17] in {
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def : WriteRes<WriteFDiv64, [p8700IssueFPUL, p8700FpuApu]>;
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def : WriteRes<WriteFSqrt64, [p8700IssueFPUL, p8700FpuApu]>;
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}
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// Bypass and advance.
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def : ReadAdvance<ReadIALU, 0>;
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def : ReadAdvance<ReadIALU32, 0>;
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def : ReadAdvance<ReadShiftImm, 0>;
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def : ReadAdvance<ReadShiftImm32, 0>;
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def : ReadAdvance<ReadShiftReg, 0>;
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def : ReadAdvance<ReadShiftReg32, 0>;
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def : ReadAdvance<ReadSHXADD, 0>;
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def : ReadAdvance<ReadSHXADD32, 0>;
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def : ReadAdvance<ReadRotateReg, 0>;
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def : ReadAdvance<ReadRotateImm, 0>;
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def : ReadAdvance<ReadCLZ, 0>;
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def : ReadAdvance<ReadCTZ, 0>;
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def : ReadAdvance<ReadCPOP, 0>;
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def : ReadAdvance<ReadRotateReg32, 0>;
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def : ReadAdvance<ReadRotateImm32, 0>;
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def : ReadAdvance<ReadCLZ32, 0>;
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def : ReadAdvance<ReadCTZ32, 0>;
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def : ReadAdvance<ReadCPOP32, 0>;
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def : ReadAdvance<ReadREV8, 0>;
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def : ReadAdvance<ReadORCB, 0>;
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def : ReadAdvance<ReadIMul, 0>;
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def : ReadAdvance<ReadIMul32, 0>;
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def : ReadAdvance<ReadIDiv, 0>;
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def : ReadAdvance<ReadIDiv32, 0>;
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def : ReadAdvance<ReadJmp, 0>;
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def : ReadAdvance<ReadJalr, 0>;
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def : ReadAdvance<ReadFMovI32ToF32, 0>;
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def : ReadAdvance<ReadFMovF32ToI32, 0>;
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def : ReadAdvance<ReadFMovI64ToF64, 0>;
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def : ReadAdvance<ReadFMovF64ToI64, 0>;
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def : ReadAdvance<ReadFSGNJ32, 0>;
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def : ReadAdvance<ReadFMinMax32, 0>;
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def : ReadAdvance<ReadFSGNJ64, 0>;
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def : ReadAdvance<ReadFMinMax64, 0>;
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def : ReadAdvance<ReadFCmp32, 0>;
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def : ReadAdvance<ReadFCmp64, 0>;
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def : ReadAdvance<ReadFCvtI32ToF32, 0>;
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def : ReadAdvance<ReadFCvtI32ToF64, 0>;
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def : ReadAdvance<ReadFCvtI64ToF32, 0>;
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def : ReadAdvance<ReadFCvtI64ToF64, 0>;
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def : ReadAdvance<ReadFCvtF32ToI32, 0>;
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def : ReadAdvance<ReadFCvtF32ToI64, 0>;
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def : ReadAdvance<ReadFCvtF32ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToI32, 0>;
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def : ReadAdvance<ReadFCvtF64ToI64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF32, 0>;
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def : ReadAdvance<ReadFAdd32, 0>;
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def : ReadAdvance<ReadFAdd64, 0>;
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def : ReadAdvance<ReadFMul32, 0>;
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def : ReadAdvance<ReadFMul64, 0>;
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def : ReadAdvance<ReadFMA32, 0>;
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def : ReadAdvance<ReadFMA32Addend, 0>;
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def : ReadAdvance<ReadFMA64, 0>;
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def : ReadAdvance<ReadFMA64Addend, 0>;
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def : ReadAdvance<ReadFDiv32, 0>;
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def : ReadAdvance<ReadFSqrt32, 0>;
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def : ReadAdvance<ReadFDiv64, 0>;
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def : ReadAdvance<ReadFSqrt64, 0>;
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def : ReadAdvance<ReadAtomicWA, 0>;
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def : ReadAdvance<ReadAtomicWD, 0>;
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def : ReadAdvance<ReadAtomicDA, 0>;
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def : ReadAdvance<ReadAtomicDD, 0>;
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def : ReadAdvance<ReadAtomicLDW, 0>;
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def : ReadAdvance<ReadAtomicLDD, 0>;
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def : ReadAdvance<ReadAtomicSTW, 0>;
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def : ReadAdvance<ReadAtomicSTD, 0>;
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def : ReadAdvance<ReadFStoreData, 0>;
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def : ReadAdvance<ReadCSR, 0>;
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def : ReadAdvance<ReadMemBase, 0>;
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def : ReadAdvance<ReadStoreData, 0>;
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def : ReadAdvance<ReadFMemBase, 0>;
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def : ReadAdvance<ReadFClass32, 0>;
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def : ReadAdvance<ReadFClass64, 0>;
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def : ReadAdvance<ReadIMinMax, 0>;
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def : ReadAdvance<ReadIRem, 0>;
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def : ReadAdvance<ReadIRem32, 0>;
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// Unsupported extensions.
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defm : UnsupportedSchedQ;
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defm : UnsupportedSchedV;
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defm : UnsupportedSchedZbc;
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defm : UnsupportedSchedZbs;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZfhmin;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedZvk;
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defm : UnsupportedSchedXsf;
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}
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