b57df56b48
There will be more schedule definitions for vendor extentions and we need to add these `UnsupportedSchedXXX` to exsiting models every time we add new schedule definitions. The fact is that each vendor will barely implement other vendors' extensions, so we can package these definitions into one.
363 lines
12 KiB
TableGen
363 lines
12 KiB
TableGen
//==- RISCVSchedSiFiveP500.td - SiFiveP500 Scheduling Defs ---*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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def SiFiveP500Model : SchedMachineModel {
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let IssueWidth = 3; // 3 micro-ops are dispatched per cycle.
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let MicroOpBufferSize = 96; // Max micro-ops that can be buffered.
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let LoadLatency = 4; // Cycles for loads to access the cache.
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let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
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let CompleteModel = false;
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}
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// The SiFiveP500 microarchitecure has 7 pipelines:
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// Three pipelines for integer operations.
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// Two pipelines for FPU operations.
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// One pipeline for Load operations.
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// One pipeline for Store operations.
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let SchedModel = SiFiveP500Model in {
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def SiFiveP500IEXQ0 : ProcResource<1>;
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def SiFiveP500IEXQ1 : ProcResource<1>;
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def SiFiveP500IEXQ2 : ProcResource<1>;
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def SiFiveP500FEXQ0 : ProcResource<1>;
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def SiFiveP500FEXQ1 : ProcResource<1>;
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def SiFiveP500Load : ProcResource<1>;
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def SiFiveP500Store : ProcResource<1>;
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def SiFiveP500IntArith : ProcResGroup<[SiFiveP500IEXQ0, SiFiveP500IEXQ1, SiFiveP500IEXQ2]>;
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defvar SiFiveP500Branch = SiFiveP500IEXQ0;
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defvar SiFiveP500SYS = SiFiveP500IEXQ1;
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defvar SiFiveP500CMOV = SiFiveP500IEXQ1;
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defvar SiFiveP500MulI2F = SiFiveP500IEXQ2;
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def SiFiveP500Div : ProcResource<1>;
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def SiFiveP500FloatArith : ProcResGroup<[SiFiveP500FEXQ0, SiFiveP500FEXQ1]>;
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defvar SiFiveP500F2I = SiFiveP500FEXQ0;
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def SiFiveP500FloatDiv : ProcResource<1>;
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let Latency = 1 in {
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// Integer arithmetic and logic
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def : WriteRes<WriteIALU, [SiFiveP500IntArith]>;
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def : WriteRes<WriteIALU32, [SiFiveP500IntArith]>;
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def : WriteRes<WriteShiftImm, [SiFiveP500IntArith]>;
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def : WriteRes<WriteShiftImm32, [SiFiveP500IntArith]>;
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def : WriteRes<WriteShiftReg, [SiFiveP500IntArith]>;
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def : WriteRes<WriteShiftReg32, [SiFiveP500IntArith]>;
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// Branching
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def : WriteRes<WriteJmp, [SiFiveP500Branch]>;
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def : WriteRes<WriteJal, [SiFiveP500Branch]>;
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def : WriteRes<WriteJalr, [SiFiveP500Branch]>;
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}
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// CMOV
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def P500WriteCMOV : SchedWriteRes<[SiFiveP500Branch, SiFiveP500CMOV]> {
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let Latency = 2;
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let NumMicroOps = 2;
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}
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def : InstRW<[P500WriteCMOV], (instrs PseudoCCMOVGPRNoX0)>;
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let Latency = 3 in {
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// Integer multiplication
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def : WriteRes<WriteIMul, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteIMul32, [SiFiveP500MulI2F]>;
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// cpop[w] look exactly like multiply.
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def : WriteRes<WriteCPOP, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteCPOP32, [SiFiveP500MulI2F]>;
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}
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// Integer division
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def : WriteRes<WriteIDiv, [SiFiveP500MulI2F, SiFiveP500Div]> {
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let Latency = 35;
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let ReleaseAtCycles = [1, 34];
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}
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def : WriteRes<WriteIDiv32, [SiFiveP500MulI2F, SiFiveP500Div]> {
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let Latency = 20;
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let ReleaseAtCycles = [1, 19];
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}
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// Integer remainder
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def : WriteRes<WriteIRem, [SiFiveP500MulI2F, SiFiveP500Div]> {
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let Latency = 35;
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let ReleaseAtCycles = [1, 34];
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}
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def : WriteRes<WriteIRem32, [SiFiveP500MulI2F, SiFiveP500Div]> {
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let Latency = 20;
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let ReleaseAtCycles = [1, 19];
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}
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let Latency = 1 in {
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// Bitmanip
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def : WriteRes<WriteRotateImm, [SiFiveP500IntArith]>;
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def : WriteRes<WriteRotateImm32, [SiFiveP500IntArith]>;
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def : WriteRes<WriteRotateReg, [SiFiveP500IntArith]>;
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def : WriteRes<WriteRotateReg32, [SiFiveP500IntArith]>;
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def : WriteRes<WriteCLZ, [SiFiveP500IntArith]>;
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def : WriteRes<WriteCLZ32, [SiFiveP500IntArith]>;
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def : WriteRes<WriteCTZ, [SiFiveP500IntArith]>;
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def : WriteRes<WriteCTZ32, [SiFiveP500IntArith]>;
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def : WriteRes<WriteORCB, [SiFiveP500IntArith]>;
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def : WriteRes<WriteIMinMax, [SiFiveP500IntArith]>;
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def : WriteRes<WriteREV8, [SiFiveP500IntArith]>;
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def : WriteRes<WriteSHXADD, [SiFiveP500IntArith]>;
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def : WriteRes<WriteSHXADD32, [SiFiveP500IntArith]>;
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}
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// Memory
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let Latency = 1 in {
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def : WriteRes<WriteSTB, [SiFiveP500Store]>;
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def : WriteRes<WriteSTH, [SiFiveP500Store]>;
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def : WriteRes<WriteSTW, [SiFiveP500Store]>;
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def : WriteRes<WriteSTD, [SiFiveP500Store]>;
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def : WriteRes<WriteFST16, [SiFiveP500Store]>;
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def : WriteRes<WriteFST32, [SiFiveP500Store]>;
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def : WriteRes<WriteFST64, [SiFiveP500Store]>;
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}
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let Latency = 4 in {
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def : WriteRes<WriteLDB, [SiFiveP500Load]>;
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def : WriteRes<WriteLDH, [SiFiveP500Load]>;
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}
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let Latency = 4 in {
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def : WriteRes<WriteLDW, [SiFiveP500Load]>;
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def : WriteRes<WriteLDD, [SiFiveP500Load]>;
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}
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let Latency = 5 in {
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def : WriteRes<WriteFLD16, [SiFiveP500Load]>;
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def : WriteRes<WriteFLD32, [SiFiveP500Load]>;
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def : WriteRes<WriteFLD64, [SiFiveP500Load]>;
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}
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// Atomic memory
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let Latency = 3 in {
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def : WriteRes<WriteAtomicSTW, [SiFiveP500Store]>;
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def : WriteRes<WriteAtomicSTD, [SiFiveP500Store]>;
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def : WriteRes<WriteAtomicW, [SiFiveP500Load]>;
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def : WriteRes<WriteAtomicD, [SiFiveP500Load]>;
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def : WriteRes<WriteAtomicLDW, [SiFiveP500Load]>;
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def : WriteRes<WriteAtomicLDD, [SiFiveP500Load]>;
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}
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// Floating point
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let Latency = 4 in {
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def : WriteRes<WriteFAdd16, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFAdd32, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFAdd64, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMul16, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMul32, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMul64, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMA16, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMA32, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMA64, [SiFiveP500FloatArith]>;
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}
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let Latency = 2 in {
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def : WriteRes<WriteFSGNJ16, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFSGNJ32, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFSGNJ64, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMinMax16, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMinMax32, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFMinMax64, [SiFiveP500FloatArith]>;
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}
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// Half precision.
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def : WriteRes<WriteFDiv16, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
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let Latency = 19;
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let ReleaseAtCycles = [1, 18];
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}
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def : WriteRes<WriteFSqrt16, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
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let Latency = 18;
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let ReleaseAtCycles = [1, 17];
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}
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// Single precision.
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def : WriteRes<WriteFDiv32, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
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let Latency = 19;
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let ReleaseAtCycles = [1, 18];
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}
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def : WriteRes<WriteFSqrt32, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
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let Latency = 18;
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let ReleaseAtCycles = [1, 17];
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}
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// Double precision
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def : WriteRes<WriteFDiv64, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
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let Latency = 33;
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let ReleaseAtCycles = [1, 32];
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}
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def : WriteRes<WriteFSqrt64, [SiFiveP500FEXQ1, SiFiveP500FloatDiv]> {
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let Latency = 33;
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let ReleaseAtCycles = [1, 32];
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}
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// Conversions
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let Latency = 2 in {
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def : WriteRes<WriteFCvtI32ToF16, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFCvtI32ToF32, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFCvtI32ToF64, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFCvtI64ToF16, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFCvtI64ToF32, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFCvtI64ToF64, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFCvtF16ToI32, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCvtF16ToI64, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCvtF16ToF32, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFCvtF16ToF64, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFCvtF32ToI32, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCvtF32ToI64, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCvtF32ToF16, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFCvtF32ToF64, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFCvtF64ToI32, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCvtF64ToI64, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCvtF64ToF16, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFCvtF64ToF32, [SiFiveP500FloatArith]>;
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def : WriteRes<WriteFClass16, [SiFiveP500F2I]>;
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def : WriteRes<WriteFClass32, [SiFiveP500F2I]>;
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def : WriteRes<WriteFClass64, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCmp16, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCmp32, [SiFiveP500F2I]>;
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def : WriteRes<WriteFCmp64, [SiFiveP500F2I]>;
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def : WriteRes<WriteFMovI16ToF16, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFMovF16ToI16, [SiFiveP500F2I]>;
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def : WriteRes<WriteFMovI32ToF32, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFMovF32ToI32, [SiFiveP500F2I]>;
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def : WriteRes<WriteFMovI64ToF64, [SiFiveP500MulI2F]>;
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def : WriteRes<WriteFMovF64ToI64, [SiFiveP500F2I]>;
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}
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// Others
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def : WriteRes<WriteCSR, [SiFiveP500SYS]>;
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def : WriteRes<WriteNop, []>;
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// FIXME: This could be better modeled by looking at the regclasses of the operands.
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def : InstRW<[WriteIALU, ReadIALU], (instrs COPY)>;
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//===----------------------------------------------------------------------===//
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// Bypass and advance
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def : ReadAdvance<ReadJmp, 0>;
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def : ReadAdvance<ReadJalr, 0>;
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def : ReadAdvance<ReadCSR, 0>;
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def : ReadAdvance<ReadStoreData, 0>;
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def : ReadAdvance<ReadMemBase, 0>;
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def : ReadAdvance<ReadIALU, 0>;
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def : ReadAdvance<ReadIALU32, 0>;
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def : ReadAdvance<ReadShiftImm, 0>;
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def : ReadAdvance<ReadShiftImm32, 0>;
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def : ReadAdvance<ReadShiftReg, 0>;
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def : ReadAdvance<ReadShiftReg32, 0>;
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def : ReadAdvance<ReadIDiv, 0>;
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def : ReadAdvance<ReadIDiv32, 0>;
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def : ReadAdvance<ReadIRem, 0>;
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def : ReadAdvance<ReadIRem32, 0>;
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def : ReadAdvance<ReadIMul, 0>;
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def : ReadAdvance<ReadIMul32, 0>;
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def : ReadAdvance<ReadAtomicWA, 0>;
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def : ReadAdvance<ReadAtomicWD, 0>;
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def : ReadAdvance<ReadAtomicDA, 0>;
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def : ReadAdvance<ReadAtomicDD, 0>;
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def : ReadAdvance<ReadAtomicLDW, 0>;
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def : ReadAdvance<ReadAtomicLDD, 0>;
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def : ReadAdvance<ReadAtomicSTW, 0>;
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def : ReadAdvance<ReadAtomicSTD, 0>;
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def : ReadAdvance<ReadFStoreData, 0>;
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def : ReadAdvance<ReadFMemBase, 0>;
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def : ReadAdvance<ReadFAdd16, 0>;
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def : ReadAdvance<ReadFAdd32, 0>;
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def : ReadAdvance<ReadFAdd64, 0>;
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def : ReadAdvance<ReadFMul16, 0>;
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def : ReadAdvance<ReadFMA16, 0>;
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def : ReadAdvance<ReadFMA16Addend, 0>;
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def : ReadAdvance<ReadFMul32, 0>;
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def : ReadAdvance<ReadFMA32, 0>;
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def : ReadAdvance<ReadFMA32Addend, 0>;
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def : ReadAdvance<ReadFMul64, 0>;
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def : ReadAdvance<ReadFMA64, 0>;
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def : ReadAdvance<ReadFMA64Addend, 0>;
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def : ReadAdvance<ReadFDiv16, 0>;
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def : ReadAdvance<ReadFDiv32, 0>;
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def : ReadAdvance<ReadFDiv64, 0>;
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def : ReadAdvance<ReadFSqrt16, 0>;
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def : ReadAdvance<ReadFSqrt32, 0>;
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def : ReadAdvance<ReadFSqrt64, 0>;
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def : ReadAdvance<ReadFCmp16, 0>;
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def : ReadAdvance<ReadFCmp32, 0>;
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def : ReadAdvance<ReadFCmp64, 0>;
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def : ReadAdvance<ReadFSGNJ16, 0>;
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def : ReadAdvance<ReadFSGNJ32, 0>;
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def : ReadAdvance<ReadFSGNJ64, 0>;
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def : ReadAdvance<ReadFMinMax16, 0>;
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def : ReadAdvance<ReadFMinMax32, 0>;
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def : ReadAdvance<ReadFMinMax64, 0>;
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def : ReadAdvance<ReadFCvtF16ToI32, 0>;
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def : ReadAdvance<ReadFCvtF16ToI64, 0>;
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def : ReadAdvance<ReadFCvtF32ToI32, 0>;
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def : ReadAdvance<ReadFCvtF32ToI64, 0>;
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def : ReadAdvance<ReadFCvtF64ToI32, 0>;
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def : ReadAdvance<ReadFCvtF64ToI64, 0>;
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def : ReadAdvance<ReadFCvtI32ToF16, 0>;
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def : ReadAdvance<ReadFCvtI32ToF32, 0>;
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def : ReadAdvance<ReadFCvtI32ToF64, 0>;
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def : ReadAdvance<ReadFCvtI64ToF16, 0>;
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def : ReadAdvance<ReadFCvtI64ToF32, 0>;
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def : ReadAdvance<ReadFCvtI64ToF64, 0>;
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def : ReadAdvance<ReadFCvtF32ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF32, 0>;
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def : ReadAdvance<ReadFCvtF16ToF32, 0>;
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def : ReadAdvance<ReadFCvtF32ToF16, 0>;
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def : ReadAdvance<ReadFCvtF16ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF16, 0>;
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def : ReadAdvance<ReadFMovF16ToI16, 0>;
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def : ReadAdvance<ReadFMovI16ToF16, 0>;
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def : ReadAdvance<ReadFMovF32ToI32, 0>;
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def : ReadAdvance<ReadFMovI32ToF32, 0>;
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def : ReadAdvance<ReadFMovF64ToI64, 0>;
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def : ReadAdvance<ReadFMovI64ToF64, 0>;
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def : ReadAdvance<ReadFClass16, 0>;
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def : ReadAdvance<ReadFClass32, 0>;
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def : ReadAdvance<ReadFClass64, 0>;
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// Bitmanip
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def : ReadAdvance<ReadRotateImm, 0>;
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def : ReadAdvance<ReadRotateImm32, 0>;
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def : ReadAdvance<ReadRotateReg, 0>;
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def : ReadAdvance<ReadRotateReg32, 0>;
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def : ReadAdvance<ReadCLZ, 0>;
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def : ReadAdvance<ReadCLZ32, 0>;
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def : ReadAdvance<ReadCTZ, 0>;
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def : ReadAdvance<ReadCTZ32, 0>;
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def : ReadAdvance<ReadCPOP, 0>;
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def : ReadAdvance<ReadCPOP32, 0>;
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def : ReadAdvance<ReadORCB, 0>;
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def : ReadAdvance<ReadIMinMax, 0>;
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def : ReadAdvance<ReadREV8, 0>;
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def : ReadAdvance<ReadSHXADD, 0>;
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def : ReadAdvance<ReadSHXADD32, 0>;
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//===----------------------------------------------------------------------===//
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// Unsupported extensions
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defm : UnsupportedSchedQ;
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defm : UnsupportedSchedV;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedZbc;
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defm : UnsupportedSchedZbs;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZfa;
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defm : UnsupportedSchedZvk;
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defm : UnsupportedSchedXsf;
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}
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