5b2c3aac90
This patch removes RSP dependencies from push and pop instructions to pretend that we have a stack engine. This does not model details like sync uops that are relevant implementation details due to complexity. This is just enabled on all X86 CPUs given LLVM does not have a scheduling model for any X86 CPU that does not have a stack engine. This fixes #152008.
85 lines
2.9 KiB
C++
85 lines
2.9 KiB
C++
//===------------------- X86CustomBehaviour.cpp -----------------*-C++ -* -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements methods from the X86CustomBehaviour class.
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///
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//===----------------------------------------------------------------------===//
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#include "X86CustomBehaviour.h"
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "TargetInfo/X86TargetInfo.h"
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#include "llvm-c/Visibility.h"
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#include "llvm/MC/TargetRegistry.h"
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namespace llvm {
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namespace mca {
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void X86InstrPostProcess::setMemBarriers(std::unique_ptr<Instruction> &Inst,
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const MCInst &MCI) {
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switch (MCI.getOpcode()) {
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case X86::MFENCE:
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Inst->setLoadBarrier(true);
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Inst->setStoreBarrier(true);
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break;
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case X86::LFENCE:
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Inst->setLoadBarrier(true);
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break;
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case X86::SFENCE:
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Inst->setStoreBarrier(true);
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break;
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}
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}
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void X86InstrPostProcess::useStackEngine(std::unique_ptr<Instruction> &Inst,
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const MCInst &MCI) {
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// TODO(boomanaiden154): We currently do not handle PUSHF/POPF because we
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// have not done the necessary benchmarking to see if they are also
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// optimized by the stack engine.
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// TODO: We currently just remove all RSP writes from stack operations. This
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// is not fully correct because we do not model sync uops which will
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// delay subsequent rsp using non-stack instructions.
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if (X86::isPOP(MCI.getOpcode()) || X86::isPUSH(MCI.getOpcode())) {
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auto *StackRegisterDef =
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llvm::find_if(Inst->getDefs(), [](const WriteState &State) {
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return State.getRegisterID() == X86::RSP;
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});
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assert(
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StackRegisterDef != Inst->getDefs().end() &&
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"Expected push instruction to implicitly use stack pointer register.");
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Inst->getDefs().erase(StackRegisterDef);
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}
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}
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void X86InstrPostProcess::postProcessInstruction(
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std::unique_ptr<Instruction> &Inst, const MCInst &MCI) {
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// Set IsALoadBarrier and IsAStoreBarrier flags.
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setMemBarriers(Inst, MCI);
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useStackEngine(Inst, MCI);
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}
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} // namespace mca
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} // namespace llvm
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using namespace llvm;
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using namespace mca;
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static InstrPostProcess *createX86InstrPostProcess(const MCSubtargetInfo &STI,
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const MCInstrInfo &MCII) {
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return new X86InstrPostProcess(STI, MCII);
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}
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/// Extern function to initialize the targets for the X86 backend
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extern "C" LLVM_C_ABI void LLVMInitializeX86TargetMCA() {
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TargetRegistry::RegisterInstrPostProcess(getTheX86_32Target(),
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createX86InstrPostProcess);
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TargetRegistry::RegisterInstrPostProcess(getTheX86_64Target(),
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createX86InstrPostProcess);
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}
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