9ae92d7056
With this change, targets are no longer required to put memory / strict-fp opcodes after special `ISD::FIRST_TARGET_MEMORY_OPCODE`/`ISD::FIRST_TARGET_STRICTFP_OPCODE` markers. This will also allow autogenerating `isTargetMemoryOpcode`/`isTargetStrictFPOpcode (#119709). Pull Request: https://github.com/llvm/llvm-project/pull/119969
50 lines
1.9 KiB
C++
50 lines
1.9 KiB
C++
//===-- X86SelectionDAGInfo.h - X86 SelectionDAG Info -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 subclass for SelectionDAGTargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_X86SELECTIONDAGINFO_H
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#define LLVM_LIB_TARGET_X86_X86SELECTIONDAGINFO_H
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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namespace llvm {
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class X86SelectionDAGInfo : public SelectionDAGTargetInfo {
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/// Returns true if it is possible for the base register to conflict with the
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/// given set of clobbers for a memory intrinsic.
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bool isBaseRegConflictPossible(SelectionDAG &DAG,
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ArrayRef<MCPhysReg> ClobberSet) const;
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public:
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explicit X86SelectionDAGInfo() = default;
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bool isTargetMemoryOpcode(unsigned Opcode) const override;
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bool isTargetStrictFPOpcode(unsigned Opcode) const override;
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SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
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SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, Align Alignment,
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bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo) const override;
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SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
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SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, Align Alignment,
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bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo,
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MachinePointerInfo SrcPtrInfo) const override;
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};
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}
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#endif
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