f78610af3f
This patch introduces a function attribute `instcombine-no-verify-fixpoint` to avoids disabling fix-point verification for unrelated tests in the same file. Address comment https://github.com/llvm/llvm-project/pull/112642#discussion_r1804714387.
110 lines
3.5 KiB
LLVM
110 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i32 @computeNumSignBits_add1(i32 %in) {
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; CHECK-LABEL: @computeNumSignBits_add1(
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[IN:%.*]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[ADD]], 43
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; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
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; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
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; CHECK-NEXT: ret i32 [[SH]]
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;
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%add = add i32 %in, 1
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%cond = icmp ule i32 %add, 42
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call void @llvm.assume(i1 %cond)
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%sh = shl i32 %add, 3
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ret i32 %sh
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}
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define i32 @computeNumSignBits_add2(i32 %in1, i32 %in2) {
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; CHECK-LABEL: @computeNumSignBits_add2(
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[IN1:%.*]], [[IN2:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[ADD]], 43
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; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
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; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[ADD]], 3
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; CHECK-NEXT: ret i32 [[SH]]
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;
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%add = add i32 %in1, %in2
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%cond = icmp ule i32 %add, 42
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call void @llvm.assume(i1 %cond)
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%sh = shl i32 %add, 3
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ret i32 %sh
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}
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define i32 @computeNumSignBits_sub1(i32 %in) {
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; CHECK-LABEL: @computeNumSignBits_sub1(
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[IN:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
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; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
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; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
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; CHECK-NEXT: ret i32 [[SH]]
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;
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%sub = sub i32 1, %in
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%cond = icmp ule i32 %sub, 42
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call void @llvm.assume(i1 %cond)
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%sh = shl i32 %sub, 3
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ret i32 %sh
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}
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define i32 @computeNumSignBits_sub2(i32 %in) {
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; CHECK-LABEL: @computeNumSignBits_sub2(
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; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[IN:%.*]], -1
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
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; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
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; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
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; CHECK-NEXT: ret i32 [[SH]]
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;
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%sub = sub i32 %in, 1
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%cond = icmp ule i32 %sub, 42
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call void @llvm.assume(i1 %cond)
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%sh = shl i32 %sub, 3
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ret i32 %sh
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}
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define i32 @computeNumSignBits_sub3(i32 %in1, i32 %in2) {
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; CHECK-LABEL: @computeNumSignBits_sub3(
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; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[IN1:%.*]], [[IN2:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SUB]], 43
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; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
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; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SUB]], 3
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; CHECK-NEXT: ret i32 [[SH]]
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;
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%sub = sub i32 %in1, %in2
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%cond = icmp ule i32 %sub, 42
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call void @llvm.assume(i1 %cond)
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%sh = shl i32 %sub, 3
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ret i32 %sh
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}
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define i32 @computeNumSignBits_mul(i32 %in1, i32 %in2) {
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; CHECK-LABEL: @computeNumSignBits_mul(
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 [[IN1:%.*]], [[IN2:%.*]]
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[MUL]], 43
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; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
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; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[MUL]], 3
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; CHECK-NEXT: ret i32 [[SH]]
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;
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%mul = mul i32 %in1, %in2
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%cond = icmp ule i32 %mul, 42
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call void @llvm.assume(i1 %cond)
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%sh = shl i32 %mul, 3
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ret i32 %sh
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}
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define i32 @computeNumSignBits_select(i32 %in, i1 %s) {
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; CHECK-LABEL: @computeNumSignBits_select(
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[S:%.*]], i32 [[IN:%.*]], i32 1
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; CHECK-NEXT: [[COND:%.*]] = icmp ult i32 [[SEL]], 43
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; CHECK-NEXT: call void @llvm.assume(i1 [[COND]])
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; CHECK-NEXT: [[SH:%.*]] = shl nuw nsw i32 [[SEL]], 3
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; CHECK-NEXT: ret i32 [[SH]]
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;
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%sel = select i1 %s, i32 %in, i32 1
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%cond = icmp ule i32 %sel, 42
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call void @llvm.assume(i1 %cond)
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%sh = shl i32 %sel, 3
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ret i32 %sh
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}
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declare void @llvm.assume(i1)
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