55311801f0
This helps handling a case where the BUILD_VECTOR has i16 element type
and i32 constant operands
t2: v8i16 = setcc t8, t17, setult:ch
t3: v8i16 = BUILD_VECTOR Constant:i32<1>, ...
t4: v8i16 = and t2, t3
t5: v8i16 = add t8, t4
This can be turned into t5: v8i16 = sub t8, t2, and allows us to remove
t3 and t4 from the DAG.
Differential Revision: https://reviews.llvm.org/D127354
20 lines
801 B
LLVM
20 lines
801 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
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define <8 x i16> @add_to_sub(<8 x i16> %0, <8 x i16> %1) {
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; CHECK-LABEL: add_to_sub:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI0_0
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; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_0]
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; CHECK-NEXT: cmhi v0.8h, v2.8h, v0.8h
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; CHECK-NEXT: cmhi v1.8h, v2.8h, v1.8h
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; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%3 = icmp ult <8 x i16> %0, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
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%4 = sext <8 x i1> %3 to <8 x i16>
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%5 = icmp ult <8 x i16> %1, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
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%6 = zext <8 x i1> %5 to <8 x i16>
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%7 = add nsw <8 x i16> %6, %4
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ret <8 x i16> %7
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}
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