d458a19317
This come from https://discourse.llvm.org/t/combining-aes-and-xor-can-be-improved-further/77248. These instructions start out with: ``` XOR Vd, Vn <some complicated math> ``` The initial XOR means that they can be treated as commutative, removing some of the unnecessary mov's introduced during register allocation.
42 lines
1.3 KiB
LLVM
42 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc %s -o - -mtriple=aarch64 -mattr=+aes | FileCheck %s
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declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %d, <16 x i8> %k)
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declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %d, <16 x i8> %k)
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define <16 x i8> @aese(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aese:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aese v0.16b, v1.16b
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; CHECK-NEXT: ret
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%r = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %r
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}
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define <16 x i8> @aese_c(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aese_c:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aese v0.16b, v1.16b
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; CHECK-NEXT: ret
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%r = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %b, <16 x i8> %a)
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ret <16 x i8> %r
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}
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define <16 x i8> @aesd(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aesd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aesd v0.16b, v1.16b
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; CHECK-NEXT: ret
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%r = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %a, <16 x i8> %b)
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ret <16 x i8> %r
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}
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define <16 x i8> @aesd_c(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: aesd_c:
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; CHECK: // %bb.0:
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; CHECK-NEXT: aesd v0.16b, v1.16b
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; CHECK-NEXT: ret
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%r = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %b, <16 x i8> %a)
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ret <16 x i8> %r
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}
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