0491d8bda7
We can generate ext from shuffles like <2, 3, 0, 1> from a single vector source. Add handling to isShuffleMaskLegal to allow DAG combines to optimize to it.
201 lines
8.4 KiB
LLVM
201 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=arm64-eabi -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=arm64-eabi -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define <8 x i8> @test_vextd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
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; CHECK-LABEL: test_vextd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #3
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @test_vextRd(<8 x i8> %tmp1, <8 x i8> %tmp2) {
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; CHECK-LABEL: test_vextRd:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v1.8b, v0.8b, #5
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4>
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @test_vextq(<16 x i8> %tmp1, <16 x i8> %tmp2) {
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; CHECK-LABEL: test_vextq:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #3
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18>
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ret <16 x i8> %tmp3
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}
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define <16 x i8> @test_vextRq(<16 x i8> %tmp1, <16 x i8> %tmp2) {
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; CHECK-LABEL: test_vextRq:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #7
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6>
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ret <16 x i8> %tmp3
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}
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define <4 x i16> @test_vextd16(<4 x i16> %tmp1, <4 x i16> %tmp2) {
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; CHECK-LABEL: test_vextd16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #6
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
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ret <4 x i16> %tmp3
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}
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define <4 x i32> @test_vextq32(<4 x i32> %tmp1, <4 x i32> %tmp2) {
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; CHECK-LABEL: test_vextq32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #12
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 3, i32 4, i32 5, i32 6>
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ret <4 x i32> %tmp3
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}
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; Undef shuffle indices should not prevent matching to VEXT:
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define <8 x i8> @test_vextd_undef(<8 x i8> %tmp1, <8 x i8> %tmp2) {
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; CHECK-LABEL: test_vextd_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #3
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10>
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ret <8 x i8> %tmp3
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}
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define <8 x i8> @test_vextd_undef2(<8 x i8> %tmp1, <8 x i8> %tmp2) {
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; CHECK-LABEL: test_vextd_undef2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.8b, v0.8b, v0.8b, #6
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 2, i32 3, i32 4, i32 5>
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @test_vextRq_undef(<16 x i8> %tmp1, <16 x i8> %tmp2) {
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; CHECK-LABEL: test_vextRq_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #7
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; CHECK-NEXT: ret
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%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 23, i32 24, i32 25, i32 26, i32 undef, i32 undef, i32 29, i32 30, i32 31, i32 0, i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6>
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @test_vextRq_undef2(<8 x i16> %tmp1) nounwind {
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; CHECK-LABEL: test_vextRq_undef2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #10
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; CHECK-NEXT: ret
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%vext = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2, i32 3, i32 4>
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ret <8 x i16> %vext;
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}
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; Tests for ReconstructShuffle function. Indices have to be carefully
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; chosen to reach lowering phase as a BUILD_VECTOR.
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; An undef in the shuffle list should still be optimizable
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define <4 x i16> @test_undef(<8 x i16> %tmp1, <8 x i16> %tmp2) {
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; CHECK-SD-LABEL: test_undef:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v1.4h
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: test_undef:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: adrp x8, .LCPI10_0
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; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
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; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI10_0]
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; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
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; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b
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; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
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; CHECK-GI-NEXT: ret
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%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <4 x i32> <i32 undef, i32 8, i32 5, i32 9>
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ret <4 x i16> %tmp3
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}
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define <2 x i64> @test_v2s64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: test_v2s64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
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; CHECK-NEXT: ret
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%s = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 3, i32 0>
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ret <2 x i64> %s
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}
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define <2 x ptr> @test_v2p0(<2 x ptr> %a, <2 x ptr> %b) {
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; CHECK-LABEL: test_v2p0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ext v0.16b, v1.16b, v0.16b, #8
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; CHECK-NEXT: ret
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%s = shufflevector <2 x ptr> %a, <2 x ptr> %b, <2 x i32> <i32 3, i32 0>
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ret <2 x ptr> %s
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}
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define <16 x i8> @reverse_vector_s8x16b(<16 x i8> noundef %x) {
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; CHECK-SD-LABEL: reverse_vector_s8x16b:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: rev64 v0.16b, v0.16b
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: reverse_vector_s8x16b:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: rev64 v1.16b, v0.16b
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; CHECK-GI-NEXT: mov d0, v1.d[1]
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; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-GI-NEXT: ret
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entry:
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%shuffle.i = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
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%shuffle.i6 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%shuffle.i7 = shufflevector <16 x i8> %shuffle.i, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%shuffle.i5 = shufflevector <8 x i8> %shuffle.i6, <8 x i8> %shuffle.i7, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %shuffle.i5
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}
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define <8 x i16> @reverse_vector_s16x8b(<8 x i16> noundef %x) {
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; CHECK-SD-LABEL: reverse_vector_s16x8b:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: rev64 v0.8h, v0.8h
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: reverse_vector_s16x8b:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: rev64 v1.8h, v0.8h
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; CHECK-GI-NEXT: mov d0, v1.d[1]
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; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-GI-NEXT: ret
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entry:
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%shuffle.i = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
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%shuffle.i6 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%shuffle.i7 = shufflevector <8 x i16> %shuffle.i, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%shuffle.i5 = shufflevector <4 x i16> %shuffle.i6, <4 x i16> %shuffle.i7, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %shuffle.i5
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}
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define <4 x i32> @reverse_vector_s32x4b(<4 x i32> noundef %x) {
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; CHECK-SD-LABEL: reverse_vector_s32x4b:
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; CHECK-SD: // %bb.0: // %entry
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; CHECK-SD-NEXT: rev64 v0.4s, v0.4s
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; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: reverse_vector_s32x4b:
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; CHECK-GI: // %bb.0: // %entry
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; CHECK-GI-NEXT: rev64 v1.4s, v0.4s
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; CHECK-GI-NEXT: mov d0, v1.d[1]
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; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
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; CHECK-GI-NEXT: ret
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entry:
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%shuffle.i = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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%shuffle.i6 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
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%shuffle.i7 = shufflevector <4 x i32> %shuffle.i, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
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%shuffle.i5 = shufflevector <2 x i32> %shuffle.i6, <2 x i32> %shuffle.i7, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %shuffle.i5
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}
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