5060f08c3a
Currently bf16 fpextend is lowered to a vector shift. Instead leave it as fpextend and have an instruction selection pattern which selects to a shift later. Doing this means that DAGCombiner patterns for fpextend will be applied, leading to better codegen. It also means that in some situations we use a mov instruction where we previously have a dup instruction, but I don't think this makes any difference.
411 lines
11 KiB
LLVM
411 lines
11 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -O0 -fast-isel -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s
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; Test fptosi
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define i32 @fptosi_wh(half %a) nounwind ssp {
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; CHECK-LABEL: fptosi_wh:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcvtzs w0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = fptosi half %a to i32
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ret i32 %conv
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}
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; Test fptoui
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define i32 @fptoui_swh(half %a) nounwind ssp {
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; CHECK-LABEL: fptoui_swh:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcvt s0, h0
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; CHECK-NEXT: fcvtzu w0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = fptoui half %a to i32
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ret i32 %conv
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}
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; Test sitofp
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define half @sitofp_hw_i1(i1 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_hw_i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sbfx w8, w0, #0, #1
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; CHECK-NEXT: scvtf s0, w8
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i1 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hw_i8(i8 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_hw_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: scvtf s0, w8
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i8 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hw_i16(i16 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_hw_i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sxth w8, w0
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; CHECK-NEXT: scvtf s0, w8
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i16 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hw_i32(i32 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_hw_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: scvtf s0, w0
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i32 %a to half
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ret half %conv
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}
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; Test sitofp
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define half @sitofp_hx(i64 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_hx:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: scvtf s0, x0
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i64 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i1(i1 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_hw_i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: and w8, w0, #0x1
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; CHECK-NEXT: ucvtf s0, w8
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i1 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i8(i8 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_hw_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: ucvtf s0, w8
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i8 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i16(i16 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_hw_i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: ucvtf s0, w8
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i16 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hw_i32(i32 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_hw_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ucvtf s0, w0
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i32 %a to half
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ret half %conv
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}
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; Test uitofp
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define half @uitofp_hx(i64 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_hx:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ucvtf s0, x0
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i64 %a to half
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ret half %conv
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}
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; Test fptosi
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define i32 @fptosi_bf(bfloat %a) nounwind ssp {
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; CHECK-LABEL: fptosi_bf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $h0
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: fcvtzs w0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = fptosi bfloat %a to i32
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ret i32 %conv
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}
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; Test fptoui
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define i32 @fptoui_sbf(bfloat %a) nounwind ssp {
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; CHECK-LABEL: fptoui_sbf:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: // kill: def $d0 killed $h0
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; CHECK-NEXT: shll v0.4s, v0.4h, #16
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; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
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; CHECK-NEXT: fcvtzu w0, s0
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; CHECK-NEXT: ret
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entry:
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%conv = fptoui bfloat %a to i32
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ret i32 %conv
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}
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; Test sitofp
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define bfloat @sitofp_bf_i1(i1 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_bf_i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sbfx w8, w0, #0, #1
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; CHECK-NEXT: scvtf s0, w8
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i1 %a to bfloat
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ret bfloat %conv
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}
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; Test sitofp
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define bfloat @sitofp_bf_i8(i8 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_bf_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sxtb w8, w0
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; CHECK-NEXT: scvtf s0, w8
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i8 %a to bfloat
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ret bfloat %conv
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}
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; Test sitofp
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define bfloat @sitofp_bf_i16(i16 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_bf_i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sxth w8, w0
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; CHECK-NEXT: scvtf s0, w8
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i16 %a to bfloat
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ret bfloat %conv
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}
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; Test sitofp
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define bfloat @sitofp_bf_i32(i32 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_bf_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: scvtf d0, w0
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; CHECK-NEXT: fcvtxn s0, d0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i32 %a to bfloat
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ret bfloat %conv
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}
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; Test sitofp
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define bfloat @sitofp_bf_i164(i64 %a) nounwind ssp {
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; CHECK-LABEL: sitofp_bf_i164:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: subs x8, x0, #0
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; CHECK-NEXT: cneg x10, x0, mi
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; CHECK-NEXT: and x8, x10, #0xfffffffffffff000
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; CHECK-NEXT: lsr x9, x10, #53
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; CHECK-NEXT: subs x9, x9, #0
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; CHECK-NEXT: csel x8, x8, x10, ne
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; CHECK-NEXT: scvtf d0, x8
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: and x9, x0, #0x8000000000000000
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; CHECK-NEXT: orr x8, x8, x9
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; CHECK-NEXT: cset w9, ne
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; CHECK-NEXT: ands x10, x10, #0xfff
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; CHECK-NEXT: csel w9, wzr, w9, eq
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; CHECK-NEXT: mov w9, w9
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; CHECK-NEXT: // kill: def $x9 killed $w9
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; CHECK-NEXT: orr x8, x8, x9
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: fcvtxn s0, d0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = sitofp i64 %a to bfloat
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ret bfloat %conv
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}
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; Test uitofp
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define bfloat @uitofp_bf_i1(i1 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_bf_i1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: and w8, w0, #0x1
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; CHECK-NEXT: ucvtf s0, w8
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i1 %a to bfloat
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ret bfloat %conv
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}
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; Test uitofp
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define bfloat @uitofp_bf_i8(i8 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_bf_i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: and w8, w0, #0xff
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; CHECK-NEXT: ucvtf s0, w8
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i8 %a to bfloat
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ret bfloat %conv
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}
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; Test uitofp
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define bfloat @uitofp_bf_i16(i16 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_bf_i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: ucvtf s0, w8
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i16 %a to bfloat
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ret bfloat %conv
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}
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; Test uitofp
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define bfloat @uitofp_bf_i32(i32 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_bf_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ucvtf d0, w0
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; CHECK-NEXT: fcvtxn s0, d0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i32 %a to bfloat
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ret bfloat %conv
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}
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; Test uitofp
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define bfloat @uitofp_bf_i64(i64 %a) nounwind ssp {
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; CHECK-LABEL: uitofp_bf_i64:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: and x8, x0, #0xfffffffffffff000
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; CHECK-NEXT: lsr x9, x0, #53
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; CHECK-NEXT: subs x9, x9, #0
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; CHECK-NEXT: csel x8, x8, x0, ne
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; CHECK-NEXT: ucvtf d0, x8
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; CHECK-NEXT: fmov x8, d0
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; CHECK-NEXT: cset w9, ne
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; CHECK-NEXT: ands x10, x0, #0xfff
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; CHECK-NEXT: csel w9, wzr, w9, eq
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; CHECK-NEXT: mov w9, w9
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; CHECK-NEXT: // kill: def $x9 killed $w9
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; CHECK-NEXT: orr x8, x8, x9
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; CHECK-NEXT: fmov d0, x8
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; CHECK-NEXT: fcvtxn s0, d0
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: ubfx w8, w9, #16, #1
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: mov w9, #32767 // =0x7fff
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: fmov s0, w8
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; CHECK-NEXT: // kill: def $h0 killed $h0 killed $s0
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; CHECK-NEXT: ret
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entry:
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%conv = uitofp i64 %a to bfloat
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ret bfloat %conv
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}
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