c649fd34e9
This patch adds a new code transformation to the `MachineSink` pass, that tries to sink copies of an instruction, when the copies can be folded into the addressing modes of load/store instructions, or replace another instruction (currently, copies into a hard register). The criteria for performing the transformation is that: * the register pressure at the sink destination block must not exceed the register pressure limits * the latency and throughput of the load/store or the copy must not deteriorate * the original instruction must be deleted Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D152828
103 lines
2.8 KiB
LLVM
103 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=arm64-eabi -mcpu=cyclone -aarch64-enable-sink-fold=true | FileCheck %s
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define i128 @shl(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x8, x1, x2
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; CHECK-NEXT: mvn w9, w2
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; CHECK-NEXT: lsr x10, x0, #1
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; CHECK-NEXT: lsr x9, x10, x9
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; CHECK-NEXT: orr x8, x8, x9
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; CHECK-NEXT: lsl x9, x0, x2
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; CHECK-NEXT: tst x2, #0x40
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; CHECK-NEXT: csel x1, x9, x8, ne
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; CHECK-NEXT: csel x0, xzr, x9, ne
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; CHECK-NEXT: ret
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%shl = shl i128 %r, %s
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ret i128 %shl
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}
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define i128 @shl_mask(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: shl_mask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl x8, x1, x2
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; CHECK-NEXT: lsr x9, x0, #1
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; CHECK-NEXT: and x10, x2, #0x3f
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; CHECK-NEXT: eor x10, x10, #0x3f
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; CHECK-NEXT: lsr x9, x9, x10
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; CHECK-NEXT: lsl x0, x0, x2
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; CHECK-NEXT: orr x1, x8, x9
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; CHECK-NEXT: ret
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%mask = and i128 %s, 63
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%shl = shl i128 %r, %mask
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ret i128 %shl
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}
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define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: ashr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, x2
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; CHECK-NEXT: mvn w9, w2
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; CHECK-NEXT: lsl x10, x1, #1
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; CHECK-NEXT: lsl x9, x10, x9
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; CHECK-NEXT: orr x8, x9, x8
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; CHECK-NEXT: asr x9, x1, x2
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; CHECK-NEXT: tst x2, #0x40
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; CHECK-NEXT: csel x0, x9, x8, ne
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; CHECK-NEXT: asr x8, x1, #63
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; CHECK-NEXT: csel x1, x8, x9, ne
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; CHECK-NEXT: ret
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%shr = ashr i128 %r, %s
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ret i128 %shr
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}
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define i128 @ashr_mask(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: ashr_mask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, x2
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; CHECK-NEXT: lsl x9, x1, #1
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; CHECK-NEXT: and x10, x2, #0x3f
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; CHECK-NEXT: eor x10, x10, #0x3f
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; CHECK-NEXT: lsl x9, x9, x10
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; CHECK-NEXT: asr x1, x1, x2
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; CHECK-NEXT: orr x0, x9, x8
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; CHECK-NEXT: ret
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%mask = and i128 %s, 63
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%shr = ashr i128 %r, %mask
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ret i128 %shr
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}
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define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, x2
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; CHECK-NEXT: mvn w9, w2
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; CHECK-NEXT: lsl x10, x1, #1
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; CHECK-NEXT: lsl x9, x10, x9
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; CHECK-NEXT: orr x8, x9, x8
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; CHECK-NEXT: lsr x9, x1, x2
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; CHECK-NEXT: tst x2, #0x40
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; CHECK-NEXT: csel x0, x9, x8, ne
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; CHECK-NEXT: csel x1, xzr, x9, ne
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; CHECK-NEXT: ret
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%shr = lshr i128 %r, %s
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ret i128 %shr
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}
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define i128 @lshr_mask(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: lshr_mask:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr x8, x0, x2
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; CHECK-NEXT: lsl x9, x1, #1
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; CHECK-NEXT: and x10, x2, #0x3f
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; CHECK-NEXT: eor x10, x10, #0x3f
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; CHECK-NEXT: lsl x9, x9, x10
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; CHECK-NEXT: lsr x1, x1, x2
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; CHECK-NEXT: orr x0, x9, x8
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; CHECK-NEXT: ret
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%mask = and i128 %s, 63
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%shr = lshr i128 %r, %mask
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ret i128 %shr
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}
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