b4d3283ab7
These were bypassing the ordinary libcall emission mechanism. Make sure we have entries in RuntimeLibcalls, which should include all possible calls the compiler could emit. Fixes not emitting the # prefix in the arm64ec case.
72 lines
1.9 KiB
LLVM
72 lines
1.9 KiB
LLVM
; RUN: llc -mtriple=arm64ec-pc-windows-msvc < %s | FileCheck %s
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define void @f1(ptr %p, i64 %n) {
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; CHECK-LABEL: "#f1":
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; CHECK: bl "#memset"
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call void @llvm.memset.p0.i64(ptr %p, i8 0, i64 %n, i1 false)
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ret void
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}
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define void @f2(ptr %p1, ptr %p2, i64 %n) {
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; CHECK-LABEL: "#f2":
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; CHECK: bl "#memcpy"
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call void @llvm.memcpy.p0.i64(ptr %p1, ptr %p2, i64 %n, i1 false)
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ret void
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}
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define double @f3(double %x, double %y) {
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; CHECK-LABEL: "#f3":
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; CHECK: b "#fmod"
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%r = frem double %x, %y
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ret double %r
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}
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define i128 @f4(i128 %x, i128 %y) {
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; CHECK-LABEL: "#f4":
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; CHECK: bl "#__divti3"
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%r = sdiv i128 %x, %y
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ret i128 %r
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}
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define i8 @f5(i8 %expected, i8 %new, ptr %ptr) "target-features"="+outline-atomics" {
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; CHECK-LABEL: "#f5":
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; CHECK: bl "#__aarch64_cas1_relax"
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%pair = cmpxchg ptr %ptr, i8 %expected, i8 %new monotonic monotonic, align 1
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%r = extractvalue { i8, i1 } %pair, 0
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ret i8 %r
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}
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define float @f6(float %val, i32 %a) {
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; CHECK-LABEL: "#f6":
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; CHECK: bl "#ldexp"
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%call = tail call fast float @llvm.ldexp.f32(float %val, i32 %a)
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ret float %call
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}
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@dst = global [512 x i8] zeroinitializer, align 1
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@src = global [512 x i8] zeroinitializer, align 1
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define void @call__arm_sc_memcpy(i64 noundef %n) #0 {
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; CHECK-LABEL: "#call__arm_sc_memcpy":
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; CHECK: bl "#__arm_sc_memcpy"
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tail call void @llvm.memcpy.p0.p0.i64(ptr align 1 @dst, ptr nonnull align 1 @src, i64 %n, i1 false)
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ret void
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}
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define void @call__arm_sc_memmove(i64 noundef %n) #0 {
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; CHECK-LABEL: "#call__arm_sc_memmove":
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; CHECK: bl "#__arm_sc_memmove"
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tail call void @llvm.memmove.p0.p0.i64(ptr align 1 @dst, ptr nonnull align 1 @src, i64 %n, i1 false)
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ret void
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}
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define void @call__arm_sc_memset(i64 noundef %n) #0 {
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; CHECK-LABEL: "#call__arm_sc_memset":
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; CHECK: bl "#__arm_sc_memset"
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tail call void @llvm.memset.p0.i64(ptr align 1 @dst, i8 2, i64 %n, i1 false)
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ret void
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}
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attributes #0 = { nounwind "aarch64_pstate_sm_enabled" "target-features"="+sme2" }
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