8837898b8d
This PR is related to #99591. In this PR, instead of modifying how the legalisation occurs depending on surrounding instructions, we refine after legalisation. This PR has two parts: * `SDPatternMatch/MatchContext`: Modify a little bit the code to match Operands (used by `m_Node(...)`) and Unary/Binary/Ternary Patterns to make it compatible with `VPMatchContext`, instead of only `m_Opc` supported. Some tests were added to ensure no regressions. * `DAGCombiner`: Add a `foldSubCtlzNot` which detect and rewrite the patterns using matching context. Remaining Tasks: - [ ] GlobalISel - [ ] Currently the pattern matching will occur even before legalisation. Should I restrict it to specific stages instead ? - [ ] Style: Add a visitVP_SUB ?? Move `foldSubCtlzNot` in another location for style consistency purpose ? @topperc --------- Co-authored-by: v01dxyz <v01dxyz@v01d.xyz>
133 lines
3.6 KiB
LLVM
133 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s --mtriple=aarch64 -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s --mtriple=aarch64 -global-isel -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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declare i8 @llvm.ctlz.i8(i8, i1)
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declare i16 @llvm.ctlz.i16(i16, i1)
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declare i32 @llvm.ctlz.i32(i32, i1)
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declare i64 @llvm.ctlz.i64(i64, i1)
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define i8 @ctlo_i8(i8 %x) {
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; CHECK-SD-LABEL: ctlo_i8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff
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; CHECK-SD-NEXT: eor w8, w8, w0, lsl #24
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; CHECK-SD-NEXT: clz w0, w8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ctlo_i8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #255 // =0xff
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; CHECK-GI-NEXT: bic w8, w8, w0
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; CHECK-GI-NEXT: clz w8, w8
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; CHECK-GI-NEXT: sub w0, w8, #24
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; CHECK-GI-NEXT: ret
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%tmp1 = xor i8 %x, -1
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%tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 false )
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ret i8 %tmp2
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}
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define i8 @ctlo_i8_undef(i8 %x) {
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; CHECK-SD-LABEL: ctlo_i8_undef:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mvn w8, w0
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; CHECK-SD-NEXT: lsl w8, w8, #24
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; CHECK-SD-NEXT: clz w0, w8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ctlo_i8_undef:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #255 // =0xff
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; CHECK-GI-NEXT: bic w8, w8, w0
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; CHECK-GI-NEXT: clz w8, w8
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; CHECK-GI-NEXT: sub w0, w8, #24
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; CHECK-GI-NEXT: ret
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%tmp1 = xor i8 %x, -1
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%tmp2 = call i8 @llvm.ctlz.i8( i8 %tmp1, i1 true )
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ret i8 %tmp2
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}
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define i16 @ctlo_i16(i16 %x) {
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; CHECK-SD-LABEL: ctlo_i16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff
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; CHECK-SD-NEXT: eor w8, w8, w0, lsl #16
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; CHECK-SD-NEXT: clz w0, w8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ctlo_i16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
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; CHECK-GI-NEXT: bic w8, w8, w0
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; CHECK-GI-NEXT: clz w8, w8
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; CHECK-GI-NEXT: sub w0, w8, #16
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; CHECK-GI-NEXT: ret
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%tmp1 = xor i16 %x, -1
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%tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 false )
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ret i16 %tmp2
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}
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define i16 @ctlo_i16_undef(i16 %x) {
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; CHECK-SD-LABEL: ctlo_i16_undef:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mvn w8, w0
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; CHECK-SD-NEXT: lsl w8, w8, #16
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; CHECK-SD-NEXT: clz w0, w8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: ctlo_i16_undef:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #65535 // =0xffff
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; CHECK-GI-NEXT: bic w8, w8, w0
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; CHECK-GI-NEXT: clz w8, w8
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; CHECK-GI-NEXT: sub w0, w8, #16
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; CHECK-GI-NEXT: ret
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%tmp1 = xor i16 %x, -1
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%tmp2 = call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true )
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ret i16 %tmp2
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}
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define i32 @ctlo_i32(i32 %x) {
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; CHECK-LABEL: ctlo_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: clz w0, w8
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; CHECK-NEXT: ret
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%tmp1 = xor i32 %x, -1
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%tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 false )
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ret i32 %tmp2
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}
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define i32 @ctlo_i32_undef(i32 %x) {
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; CHECK-LABEL: ctlo_i32_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn w8, w0
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; CHECK-NEXT: clz w0, w8
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; CHECK-NEXT: ret
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%tmp1 = xor i32 %x, -1
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%tmp2 = call i32 @llvm.ctlz.i32( i32 %tmp1, i1 true )
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ret i32 %tmp2
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}
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define i64 @ctlo_i64(i64 %x) {
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; CHECK-LABEL: ctlo_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x8, x0
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; CHECK-NEXT: clz x0, x8
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; CHECK-NEXT: ret
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%tmp1 = xor i64 %x, -1
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%tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 false )
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ret i64 %tmp2
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}
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define i64 @ctlo_i64_undef(i64 %x) {
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; CHECK-LABEL: ctlo_i64_undef:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x8, x0
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; CHECK-NEXT: clz x0, x8
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; CHECK-NEXT: ret
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%tmp1 = xor i64 %x, -1
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%tmp2 = call i64 @llvm.ctlz.i64( i64 %tmp1, i1 true )
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ret i64 %tmp2
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}
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