db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
129 lines
3.1 KiB
LLVM
129 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-- -o - %s | FileCheck %s
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define i32 @and_commute0(i32 %x, i32 %y) {
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; CHECK-LABEL: and_commute0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, w1
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; CHECK-NEXT: ret
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%b = and i32 %x, %y
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%b2 = and i32 %x, %b
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ret i32 %b2
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}
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define i128 @and_commute1(i128 %x, i128 %y) {
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; CHECK-LABEL: and_commute1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and x1, x3, x1
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; CHECK-NEXT: and x0, x2, x0
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; CHECK-NEXT: ret
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%b = and i128 %y, %x
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%b2 = and i128 %x, %b
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ret i128 %b2
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}
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define <4 x i32> @and_commute2(<4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: and_commute2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%b = and <4 x i32> %x, %y
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%b2 = and <4 x i32> %b, %x
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ret <4 x i32> %b2
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}
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define <8 x i16> @and_commute3(<8 x i16> %x, <8 x i16> %y) {
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; CHECK-LABEL: and_commute3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%b = and <8 x i16> %y, %x
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%b2 = and <8 x i16> %b, %x
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ret <8 x i16> %b2
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}
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define i16 @or_commute0(i16 %x, i16 %y) {
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; CHECK-LABEL: or_commute0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, w0, w1
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; CHECK-NEXT: ret
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%b = or i16 %x, %y
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%b2 = or i16 %x, %b
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ret i16 %b2
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}
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define i8 @or_commute1(i8 %x, i8 %y) {
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; CHECK-LABEL: or_commute1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr w0, w1, w0
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; CHECK-NEXT: ret
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%b = or i8 %y, %x
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%b2 = or i8 %x, %b
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ret i8 %b2
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}
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define <2 x i64> @or_commute2(<2 x i64> %x, <2 x i64> %y) {
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; CHECK-LABEL: or_commute2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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%b = or <2 x i64> %x, %y
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%b2 = or <2 x i64> %b, %x
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ret <2 x i64> %b2
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}
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define <8 x i64> @or_commute3(<8 x i64> %x, <8 x i64> %y) {
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; CHECK-LABEL: or_commute3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: orr v2.16b, v6.16b, v2.16b
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; CHECK-NEXT: orr v0.16b, v4.16b, v0.16b
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; CHECK-NEXT: orr v1.16b, v5.16b, v1.16b
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; CHECK-NEXT: orr v3.16b, v7.16b, v3.16b
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; CHECK-NEXT: ret
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%b = or <8 x i64> %y, %x
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%b2 = or <8 x i64> %b, %x
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ret <8 x i64> %b2
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}
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define <16 x i8> @xor_commute0(<16 x i8> %x, <16 x i8> %y) {
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; CHECK-LABEL: xor_commute0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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%b = xor <16 x i8> %x, %y
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%b2 = xor <16 x i8> %x, %b
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ret <16 x i8> %b2
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}
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define <8 x i32> @xor_commute1(<8 x i32> %x, <8 x i32> %y) {
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; CHECK-LABEL: xor_commute1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov v1.16b, v3.16b
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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%b = xor <8 x i32> %y, %x
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%b2 = xor <8 x i32> %x, %b
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ret <8 x i32> %b2
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}
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define i64 @xor_commute2(i64 %x, i64 %y) {
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; CHECK-LABEL: xor_commute2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x0, x1
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; CHECK-NEXT: ret
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%b = xor i64 %x, %y
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%b2 = xor i64 %b, %x
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ret i64 %b2
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}
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define i78 @xor_commute3(i78 %x, i78 %y) {
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; CHECK-LABEL: xor_commute3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x1, x3
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; CHECK-NEXT: mov x0, x2
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; CHECK-NEXT: ret
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%b = xor i78 %y, %x
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%b2 = xor i78 %b, %x
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ret i78 %b2
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}
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