db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
47 lines
1.3 KiB
LLVM
47 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s
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; When lowering the LLVM IR to MIR, transient COPY instructions are generated
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; to copy parameters from physical registers to virtual registers. Wrong
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; handling of transient instructions in MachineCombiner can fail the forllowing
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; transformation.
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; A - (B + C) ==> (A - B) - C
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; 32 bit version.
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define i32 @test1(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: eor w8, w1, w0, lsl #8
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; CHECK-NEXT: sub w9, w2, w0
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; CHECK-NEXT: sub w9, w9, w8
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; CHECK-NEXT: eor w0, w9, w8, asr #13
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; CHECK-NEXT: ret
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entry:
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%shl = shl i32 %a, 8
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%xor = xor i32 %shl, %b
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%add = add i32 %xor, %a
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%sub = sub i32 %c, %add
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%shr = ashr i32 %xor, 13
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%xor2 = xor i32 %sub, %shr
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ret i32 %xor2
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}
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; 64 bit version.
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define i64 @test2(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: eor x8, x1, x0, lsl #8
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; CHECK-NEXT: sub x9, x2, x0
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; CHECK-NEXT: sub x9, x9, x8
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; CHECK-NEXT: eor x0, x9, x8, asr #13
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; CHECK-NEXT: ret
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entry:
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%shl = shl i64 %a, 8
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%xor = xor i64 %shl, %b
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%add = add i64 %xor, %a
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%sub = sub i64 %c, %add
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%shr = ashr i64 %xor, 13
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%xor2 = xor i64 %sub, %shr
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ret i64 %xor2
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}
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