4cc152c823
This reverts partially this commit 0b73b5af60f2c544892b9dd68b4fa43eeff52fc1. This is not a clear revert because other changes already landed. CFI directives like `.cfi_negate_ra_state` must be emitted after the instruction. If the execution is stopped before the `paciasp` instruction is executed the debugger/unwinder would try to authenticated the return address as the `.cfi_negate_ra_state` already indicates it got signed. fixes: #137802
169 lines
5.1 KiB
LLVM
169 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 %s -o - | \
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; RUN: FileCheck %s --check-prefixes CHECK,V8A
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; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 -mattr=+v8.3a %s -o - | \
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; RUN: FileCheck %s --check-prefixes CHECK,V83A
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define void @a() "sign-return-address"="all" {
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; V8A-LABEL: a:
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; V8A: // %bb.0:
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; V8A-NEXT: hint #25
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; V8A-NEXT: .cfi_negate_ra_state
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; V8A-NEXT: sub sp, sp, #32
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; V8A-NEXT: .cfi_def_cfa_offset 32
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; V8A-NEXT: mov w8, #1 // =0x1
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; V8A-NEXT: mov w9, #2 // =0x2
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; V8A-NEXT: stp w9, w8, [sp, #24]
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; V8A-NEXT: mov w9, #3 // =0x3
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; V8A-NEXT: mov w8, #4 // =0x4
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; V8A-NEXT: stp w8, w9, [sp, #16]
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; V8A-NEXT: mov w9, #5 // =0x5
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; V8A-NEXT: mov w8, #6 // =0x6
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; V8A-NEXT: stp w8, w9, [sp, #8]
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; V8A-NEXT: add sp, sp, #32
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; V8A-NEXT: hint #29
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; V8A-NEXT: ret
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;
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; V83A-LABEL: a:
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; V83A: // %bb.0:
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; V83A-NEXT: paciasp
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; V83A-NEXT: .cfi_negate_ra_state
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; V83A-NEXT: sub sp, sp, #32
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; V83A-NEXT: .cfi_def_cfa_offset 32
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; V83A-NEXT: mov w8, #1 // =0x1
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; V83A-NEXT: mov w9, #2 // =0x2
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; V83A-NEXT: stp w9, w8, [sp, #24]
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; V83A-NEXT: mov w9, #3 // =0x3
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; V83A-NEXT: mov w8, #4 // =0x4
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; V83A-NEXT: stp w8, w9, [sp, #16]
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; V83A-NEXT: mov w9, #5 // =0x5
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; V83A-NEXT: mov w8, #6 // =0x6
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; V83A-NEXT: stp w8, w9, [sp, #8]
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; V83A-NEXT: add sp, sp, #32
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; V83A-NEXT: retaa
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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store i32 1, ptr %1, align 4
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store i32 2, ptr %2, align 4
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store i32 3, ptr %3, align 4
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store i32 4, ptr %4, align 4
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store i32 5, ptr %5, align 4
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store i32 6, ptr %6, align 4
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ret void
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}
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define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" {
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; V8A-LABEL: b:
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; V8A: // %bb.0:
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; V8A-NEXT: .cfi_b_key_frame
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; V8A-NEXT: hint #27
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; V8A-NEXT: .cfi_negate_ra_state
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; V8A-NEXT: sub sp, sp, #32
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; V8A-NEXT: .cfi_def_cfa_offset 32
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; V8A-NEXT: mov w8, #1 // =0x1
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; V8A-NEXT: mov w9, #2 // =0x2
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; V8A-NEXT: stp w9, w8, [sp, #24]
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; V8A-NEXT: mov w9, #3 // =0x3
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; V8A-NEXT: mov w8, #4 // =0x4
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; V8A-NEXT: stp w8, w9, [sp, #16]
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; V8A-NEXT: mov w9, #5 // =0x5
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; V8A-NEXT: mov w8, #6 // =0x6
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; V8A-NEXT: stp w8, w9, [sp, #8]
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; V8A-NEXT: add sp, sp, #32
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; V8A-NEXT: hint #31
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; V8A-NEXT: ret
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;
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; V83A-LABEL: b:
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; V83A: // %bb.0:
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; V83A-NEXT: .cfi_b_key_frame
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; V83A-NEXT: pacibsp
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; V83A-NEXT: .cfi_negate_ra_state
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; V83A-NEXT: sub sp, sp, #32
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; V83A-NEXT: .cfi_def_cfa_offset 32
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; V83A-NEXT: mov w8, #1 // =0x1
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; V83A-NEXT: mov w9, #2 // =0x2
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; V83A-NEXT: stp w9, w8, [sp, #24]
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; V83A-NEXT: mov w9, #3 // =0x3
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; V83A-NEXT: mov w8, #4 // =0x4
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; V83A-NEXT: stp w8, w9, [sp, #16]
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; V83A-NEXT: mov w9, #5 // =0x5
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; V83A-NEXT: mov w8, #6 // =0x6
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; V83A-NEXT: stp w8, w9, [sp, #8]
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; V83A-NEXT: add sp, sp, #32
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; V83A-NEXT: retab
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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store i32 1, ptr %1, align 4
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store i32 2, ptr %2, align 4
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store i32 3, ptr %3, align 4
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store i32 4, ptr %4, align 4
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store i32 5, ptr %5, align 4
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store i32 6, ptr %6, align 4
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ret void
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}
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define void @c() "sign-return-address"="all" {
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; V8A-LABEL: c:
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; V8A: // %bb.0:
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; V8A-NEXT: hint #25
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; V8A-NEXT: .cfi_negate_ra_state
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; V8A-NEXT: sub sp, sp, #32
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; V8A-NEXT: .cfi_def_cfa_offset 32
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; V8A-NEXT: mov w8, #1 // =0x1
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; V8A-NEXT: mov w9, #2 // =0x2
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; V8A-NEXT: stp w9, w8, [sp, #24]
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; V8A-NEXT: mov w9, #3 // =0x3
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; V8A-NEXT: mov w8, #4 // =0x4
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; V8A-NEXT: stp w8, w9, [sp, #16]
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; V8A-NEXT: mov w9, #5 // =0x5
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; V8A-NEXT: mov w8, #6 // =0x6
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; V8A-NEXT: stp w8, w9, [sp, #8]
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; V8A-NEXT: add sp, sp, #32
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; V8A-NEXT: hint #29
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; V8A-NEXT: ret
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;
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; V83A-LABEL: c:
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; V83A: // %bb.0:
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; V83A-NEXT: paciasp
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; V83A-NEXT: .cfi_negate_ra_state
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; V83A-NEXT: sub sp, sp, #32
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; V83A-NEXT: .cfi_def_cfa_offset 32
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; V83A-NEXT: mov w8, #1 // =0x1
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; V83A-NEXT: mov w9, #2 // =0x2
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; V83A-NEXT: stp w9, w8, [sp, #24]
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; V83A-NEXT: mov w9, #3 // =0x3
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; V83A-NEXT: mov w8, #4 // =0x4
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; V83A-NEXT: stp w8, w9, [sp, #16]
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; V83A-NEXT: mov w9, #5 // =0x5
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; V83A-NEXT: mov w8, #6 // =0x6
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; V83A-NEXT: stp w8, w9, [sp, #8]
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; V83A-NEXT: add sp, sp, #32
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; V83A-NEXT: retaa
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%1 = alloca i32, align 4
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%2 = alloca i32, align 4
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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%5 = alloca i32, align 4
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%6 = alloca i32, align 4
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store i32 1, ptr %1, align 4
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store i32 2, ptr %2, align 4
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store i32 3, ptr %3, align 4
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store i32 4, ptr %4, align 4
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store i32 5, ptr %5, align 4
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store i32 6, ptr %6, align 4
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ret void
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}
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; CHECK-NOT: OUTLINED_FUNCTION_0:
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; CHECK-NOT: // -- Begin function
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}
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