db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
170 lines
4.9 KiB
LLVM
170 lines
4.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
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define <4 x i32> @t1(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: t1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t1 = icmp sgt <4 x i32> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %t2
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}
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define <4 x i32> @t2(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: t2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t1 = icmp slt <4 x i32> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %t2
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}
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define <4 x i32> @t3(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: t3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%t1 = icmp ugt <4 x i32> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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ret <4 x i32> %t2
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}
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define <8 x i8> @t4(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: t4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umin v0.8b, v0.8b, v1.8b
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; CHECK-NEXT: ret
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%t1 = icmp ult <8 x i8> %a, %b
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%t2 = select <8 x i1> %t1, <8 x i8> %a, <8 x i8> %b
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ret <8 x i8> %t2
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}
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define <4 x i16> @t5(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: t5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smin v0.4h, v1.4h, v0.4h
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; CHECK-NEXT: ret
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%t1 = icmp sgt <4 x i16> %b, %a
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%t2 = select <4 x i1> %t1, <4 x i16> %a, <4 x i16> %b
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ret <4 x i16> %t2
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}
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define <2 x i32> @t6(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: t6:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smax v0.2s, v1.2s, v0.2s
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; CHECK-NEXT: ret
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%t1 = icmp slt <2 x i32> %b, %a
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%t2 = select <2 x i1> %t1, <2 x i32> %a, <2 x i32> %b
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ret <2 x i32> %t2
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}
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define <16 x i8> @t7(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: t7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umin v0.16b, v1.16b, v0.16b
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; CHECK-NEXT: ret
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%t1 = icmp ugt <16 x i8> %b, %a
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%t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
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ret <16 x i8> %t2
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}
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define <8 x i16> @t8(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: t8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umax v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: ret
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%t1 = icmp ult <8 x i16> %b, %a
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%t2 = select <8 x i1> %t1, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %t2
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}
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define <4 x i32> @t9(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: t9:
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; CHECK: // %bb.0:
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; CHECK-NEXT: umin v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: ret
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%t1 = icmp ugt <4 x i32> %b, %a
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%t2 = select <4 x i1> %t1, <4 x i32> %a, <4 x i32> %b
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%t3 = icmp sge <4 x i32> %t2, %c
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%t4 = select <4 x i1> %t3, <4 x i32> %t2, <4 x i32> %c
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ret <4 x i32> %t4
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}
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define <8 x i32> @t10(<8 x i32> %a, <8 x i32> %b) {
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; CHECK-LABEL: t10:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smax v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: smax v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: ret
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%t1 = icmp sgt <8 x i32> %a, %b
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%t2 = select <8 x i1> %t1, <8 x i32> %a, <8 x i32> %b
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ret <8 x i32> %t2
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}
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define <16 x i32> @t11(<16 x i32> %a, <16 x i32> %b) {
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; CHECK-LABEL: t11:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smin v2.4s, v2.4s, v6.4s
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; CHECK-NEXT: smin v0.4s, v0.4s, v4.4s
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; CHECK-NEXT: smin v1.4s, v1.4s, v5.4s
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; CHECK-NEXT: smin v3.4s, v3.4s, v7.4s
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; CHECK-NEXT: ret
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%t1 = icmp sle <16 x i32> %a, %b
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%t2 = select <16 x i1> %t1, <16 x i32> %a, <16 x i32> %b
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ret <16 x i32> %t2
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}
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; The icmp is used by two instructions, so don't produce a umin node.
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define <16 x i8> @t12(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: t12:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmhi v2.16b, v1.16b, v0.16b
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: sub v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%t1 = icmp ugt <16 x i8> %b, %a
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%t2 = select <16 x i1> %t1, <16 x i8> %a, <16 x i8> %b
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%t3 = zext <16 x i1> %t1 to <16 x i8>
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%t4 = add <16 x i8> %t3, %t2
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ret <16 x i8> %t4
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}
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define <1 x i64> @t13(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: t13:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmhi d2, d1, d0
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; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: ret
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%t1 = icmp ult <1 x i64> %a, %b
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%t2 = select <1 x i1> %t1, <1 x i64> %a, <1 x i64> %b
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ret <1 x i64> %t2
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}
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define <2 x i64> @t14(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: t14:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmhi v2.2d, v0.2d, v1.2d
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; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b
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; CHECK-NEXT: ret
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%t1 = icmp ugt <2 x i64> %a, %b
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%t2 = select <2 x i1> %t1, <2 x i64> %a, <2 x i64> %b
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ret <2 x i64> %t2
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}
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define <4 x i64> @t15(<4 x i64> %a, <4 x i64> %b) {
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; CHECK-LABEL: t15:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmhi v4.2d, v3.2d, v1.2d
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; CHECK-NEXT: cmhi v5.2d, v2.2d, v0.2d
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; CHECK-NEXT: bif v1.16b, v3.16b, v4.16b
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; CHECK-NEXT: bif v0.16b, v2.16b, v5.16b
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; CHECK-NEXT: ret
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%t1 = icmp ule <4 x i64> %a, %b
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%t2 = select <4 x i1> %t1, <4 x i64> %a, <4 x i64> %b
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ret <4 x i64> %t2
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}
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