2ec91a5ec4
This is essentially from performAddSubCombine. addsub.ll has been cleaned up a little in the process.
171 lines
4.5 KiB
LLVM
171 lines
4.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-elf < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-none-elf -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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declare i64 @llvm.abs.i64(i64, i1 immarg)
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define i64 @neg_abs64(i64 %x) {
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; CHECK-SD-LABEL: neg_abs64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmp x0, #0
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; CHECK-SD-NEXT: cneg x0, x0, pl
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: neg_abs64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp x0, #0
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; CHECK-GI-NEXT: cneg x8, x0, le
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; CHECK-GI-NEXT: neg x0, x8
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; CHECK-GI-NEXT: ret
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%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
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%neg = sub nsw i64 0, %abs
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ret i64 %neg
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}
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declare i32 @llvm.abs.i32(i32, i1 immarg)
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define i32 @neg_abs32(i32 %x) {
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; CHECK-SD-LABEL: neg_abs32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: cneg w0, w0, pl
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: neg_abs32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: cneg w8, w0, le
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; CHECK-GI-NEXT: neg w0, w8
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; CHECK-GI-NEXT: ret
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%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
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%neg = sub nsw i32 0, %abs
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ret i32 %neg
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}
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declare i16 @llvm.abs.i16(i16, i1 immarg)
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define i16 @neg_abs16(i16 %x) {
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; CHECK-SD-LABEL: neg_abs16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sbfx w8, w0, #15, #1
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; CHECK-SD-NEXT: eor w9, w0, w8
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; CHECK-SD-NEXT: sub w0, w8, w9
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: neg_abs16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sxth w8, w0
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; CHECK-GI-NEXT: cmp w8, #0
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; CHECK-GI-NEXT: cneg w8, w0, le
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; CHECK-GI-NEXT: neg w0, w8
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; CHECK-GI-NEXT: ret
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%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
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%neg = sub nsw i16 0, %abs
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ret i16 %neg
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}
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declare i128 @llvm.abs.i128(i128, i1 immarg)
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define i128 @neg_abs128(i128 %x) {
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; CHECK-SD-LABEL: neg_abs128:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr x8, x1, #63
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; CHECK-SD-NEXT: eor x9, x0, x8
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; CHECK-SD-NEXT: eor x10, x1, x8
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; CHECK-SD-NEXT: subs x0, x8, x9
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; CHECK-SD-NEXT: sbc x1, x8, x10
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: neg_abs128:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: asr x8, x1, #63
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; CHECK-GI-NEXT: adds x9, x0, x8
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; CHECK-GI-NEXT: adc x10, x1, x8
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; CHECK-GI-NEXT: eor x9, x9, x8
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; CHECK-GI-NEXT: eor x8, x10, x8
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; CHECK-GI-NEXT: negs x0, x9
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; CHECK-GI-NEXT: ngc x1, x8
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; CHECK-GI-NEXT: ret
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%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
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%neg = sub nsw i128 0, %abs
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ret i128 %neg
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}
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define i64 @abs64(i64 %x) {
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; CHECK-SD-LABEL: abs64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmp x0, #0
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; CHECK-SD-NEXT: cneg x0, x0, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp x0, #0
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; CHECK-GI-NEXT: cneg x0, x0, le
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; CHECK-GI-NEXT: ret
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%abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
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ret i64 %abs
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}
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define i32 @abs32(i32 %x) {
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; CHECK-SD-LABEL: abs32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: cneg w0, w0, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: cneg w0, w0, le
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; CHECK-GI-NEXT: ret
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%abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
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ret i32 %abs
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}
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define i16 @abs16(i16 %x) {
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; CHECK-SD-LABEL: abs16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sxth w8, w0
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; CHECK-SD-NEXT: cmp w8, #0
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; CHECK-SD-NEXT: cneg w0, w8, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sxth w8, w0
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; CHECK-GI-NEXT: cmp w8, #0
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; CHECK-GI-NEXT: cneg w0, w0, le
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; CHECK-GI-NEXT: ret
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%abs = tail call i16 @llvm.abs.i16(i16 %x, i1 true)
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ret i16 %abs
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}
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define i128 @abs128(i128 %x) {
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; CHECK-SD-LABEL: abs128:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr x8, x1, #63
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; CHECK-SD-NEXT: eor x9, x0, x8
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; CHECK-SD-NEXT: eor x10, x1, x8
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; CHECK-SD-NEXT: subs x0, x9, x8
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; CHECK-SD-NEXT: sbc x1, x10, x8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: abs128:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: asr x8, x1, #63
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; CHECK-GI-NEXT: adds x9, x0, x8
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; CHECK-GI-NEXT: adc x10, x1, x8
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; CHECK-GI-NEXT: eor x0, x9, x8
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; CHECK-GI-NEXT: eor x1, x10, x8
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; CHECK-GI-NEXT: ret
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%abs = tail call i128 @llvm.abs.i128(i128 %x, i1 true)
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ret i128 %abs
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}
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