b6f65f07bc
Implement proper splitting functions for PARTIAL_REDUCE_MLA ISD nodes. This makes the udot_8to64 and sdot_8to64 tests generate dot product instructions for when the new ISD nodes are used. --------- Co-authored-by: James Chesterman <james.chesterman@arm.com>
84 lines
3.9 KiB
LLVM
84 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -force-vector-interleave=1 -o - %s | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-none-unknown-elf"
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define <4 x i32> @partial_reduce_add_fixed(<4 x i32> %accumulator, <4 x i32> %0) #0 {
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; CHECK-LABEL: partial_reduce_add_fixed:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v4i32.v4i32(<4 x i32> %accumulator, <4 x i32> %0)
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ret <4 x i32> %partial.reduce
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}
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define <4 x i32> @partial_reduce_add_fixed_half(<4 x i32> %accumulator, <8 x i32> %0) #0 {
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; CHECK-LABEL: partial_reduce_add_fixed_half:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <4 x i32> @llvm.experimental.vector.partial.reduce.add.v4i32.v4i32.v8i32(<4 x i32> %accumulator, <8 x i32> %0)
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ret <4 x i32> %partial.reduce
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}
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define <vscale x 4 x i32> @partial_reduce_add(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0) #0 {
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; CHECK-LABEL: partial_reduce_add:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv4i32(<vscale x 4 x i32> %accumulator, <vscale x 4 x i32> %0)
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ret <vscale x 4 x i32> %partial.reduce
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}
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define <vscale x 4 x i32> @partial_reduce_add_half(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0) #0 {
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; CHECK-LABEL: partial_reduce_add_half:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: add z0.s, z0.s, z2.s
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv8i32(<vscale x 4 x i32> %accumulator, <vscale x 8 x i32> %0)
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ret <vscale x 4 x i32> %partial.reduce
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}
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define <vscale x 4 x i32> @partial_reduce_add_quart(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0) #0 {
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; CHECK-LABEL: partial_reduce_add_quart:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add z2.s, z2.s, z3.s
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; CHECK-NEXT: add z0.s, z0.s, z1.s
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; CHECK-NEXT: add z0.s, z0.s, z2.s
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; CHECK-NEXT: add z0.s, z0.s, z4.s
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv16i32(<vscale x 4 x i32> %accumulator, <vscale x 16 x i32> %0)
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ret <vscale x 4 x i32> %partial.reduce
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}
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define <vscale x 8 x i32> @partial_reduce_add_half_8(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0) #0 {
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; CHECK-LABEL: partial_reduce_add_half_8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add z0.s, z0.s, z2.s
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; CHECK-NEXT: add z1.s, z1.s, z4.s
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; CHECK-NEXT: add z0.s, z0.s, z3.s
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; CHECK-NEXT: add z1.s, z1.s, z5.s
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; CHECK-NEXT: ret
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entry:
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%partial.reduce = call <vscale x 8 x i32> @llvm.experimental.vector.partial.reduce.add.nxv8i32.nxv8i32.nxv16i32(<vscale x 8 x i32> %accumulator, <vscale x 16 x i32> %0)
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ret <vscale x 8 x i32> %partial.reduce
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}
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declare <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv8i32(<vscale x 4 x i32>, <vscale x 8 x i32>)
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declare <vscale x 4 x i32> @llvm.experimental.vector.partial.reduce.add.nxv4i32.nxv4i32.nxv16i32(<vscale x 4 x i32>, <vscale x 16 x i32>)
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declare <vscale x 8 x i32> @llvm.experimental.vector.partial.reduce.add.nxv8i32.nxv8i32.nxv16i32(<vscale x 8 x i32>, <vscale x 16 x i32>)
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declare i32 @llvm.vector.reduce.add.nxv4i32(<vscale x 4 x i32>)
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declare i32 @llvm.vector.reduce.add.nxv8i32(<vscale x 8 x i32>)
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attributes #0 = { "target-features"="+sve2" }
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