e6382f2111
The pattern ```LLVM %shl = shl i32 %x, 31 %ashr = ashr i32 %shl, 31 ``` would be combined to `SIGN_EXTEND_INREG %x, ValueType:ch:i1` by SelectionDAG. However InstCombine normalizes this pattern to: ```LLVM %and = and i32 %x, 1 %neg = sub i32 0, %and ``` This adds matching code to DAGCombiner to catch this variant as well.
26 lines
810 B
LLVM
26 lines
810 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
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define i62 @f(i1 %0) {
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; CHECK-LABEL: f:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-NEXT: sbfx x8, x0, #0, #1
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; CHECK-NEXT: mov x9, #4611686018427387903 // =0x3fffffffffffffff
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; CHECK-NEXT: bics xzr, x9, x8
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%2 = zext i1 %0 to i59
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%3 = call { i59, i1 } @llvm.umul.with.overflow.i59(i59 %2, i59 -1)
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%4 = extractvalue { i59, i1 } %3, 0
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%5 = trunc i59 %4 to i21
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%6 = trunc i59 %4 to i21
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%7 = ashr i21 %5, %6
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%8 = sext i21 %7 to i62
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%9 = icmp ugt i62 -1, %8
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%10 = zext i1 %9 to i62
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ret i62 %10
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}
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declare { i59, i1 } @llvm.umul.with.overflow.i59(i59, i59)
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