e6ada7162e
Change the spill weight calculations for `optsize` functions to remove the block frequency multiplier. For those functions, we do not want to consider the runtime cost of spilling, only the codesize cost. I built a large app with the basic and greedy (default) register allocator enabled. | Regalloc Type | Uncompressed Size Delta | Compressed Size Delta | | - | - | - | | Basic | -303.8 KiB (-0.23%) | -232.0 KiB (-0.39%) | | Greedy | 159.1 KiB (0.12%) | 130.1 KiB (0.22%) | Since I only saw a size win with the basic register allocator, I decided to only change the behavior for that type.
169 lines
5.5 KiB
LLVM
169 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 -regalloc=basic | FileCheck %s
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; Test that the register allocator behaves differently with minsize functions.
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declare void @foo(i32, ptr)
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define void @optsize(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %arg5, i1 %arg6) minsize {
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; CHECK-LABEL: optsize:
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; CHECK: // %bb.0: // %bb
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; CHECK-NEXT: stp x30, x23, [sp, #-48]! // 16-byte Folded Spill
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; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: .cfi_offset w21, -24
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; CHECK-NEXT: .cfi_offset w22, -32
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; CHECK-NEXT: .cfi_offset w23, -40
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; CHECK-NEXT: .cfi_offset w30, -48
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; CHECK-NEXT: mov w23, w5
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; CHECK-NEXT: mov x22, x4
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; CHECK-NEXT: mov x21, x3
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; CHECK-NEXT: mov x20, x2
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; CHECK-NEXT: mov w19, w1
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; CHECK-NEXT: .LBB0_1: // %bb8
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cbz w19, .LBB0_1
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; CHECK-NEXT: // %bb.2: // %bb8
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; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: cmp w19, #39
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; CHECK-NEXT: b.eq .LBB0_6
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; CHECK-NEXT: // %bb.3: // %bb8
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; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: cmp w19, #34
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; CHECK-NEXT: b.eq .LBB0_6
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; CHECK-NEXT: // %bb.4: // %bb8
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; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: cmp w19, #10
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; CHECK-NEXT: b.ne .LBB0_1
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; CHECK-NEXT: // %bb.5: // %bb9
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; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: str wzr, [x20]
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; CHECK-NEXT: b .LBB0_1
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; CHECK-NEXT: .LBB0_6: // %bb10
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; CHECK-NEXT: // in Loop: Header=BB0_1 Depth=1
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; CHECK-NEXT: mov w0, w23
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; CHECK-NEXT: mov x1, x21
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; CHECK-NEXT: str wzr, [x22]
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: b .LBB0_1
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bb:
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br label %bb7
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bb7: ; preds = %bb13, %bb
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%phi = phi i32 [ 0, %bb ], [ %spec.select, %bb13 ]
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br label %bb8
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bb8: ; preds = %bb10, %bb9, %bb8, %bb7
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switch i32 %arg1, label %bb8 [
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i32 10, label %bb9
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i32 1, label %bb16
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i32 0, label %bb13
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i32 39, label %bb10
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i32 34, label %bb10
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]
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bb9: ; preds = %bb8
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store i32 0, ptr %arg2, align 4
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br label %bb8
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bb10: ; preds = %bb8, %bb8
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store i32 0, ptr %arg4, align 4
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tail call void @foo(i32 %arg5, ptr %arg3)
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br label %bb8
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bb13: ; preds = %bb8
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%not.arg6 = xor i1 %arg6, true
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%spec.select = zext i1 %not.arg6 to i32
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br label %bb7
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bb16: ; preds = %bb8
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unreachable
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}
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define void @optspeed(i32 %arg, i32 %arg1, ptr %arg2, ptr %arg3, ptr %arg4, i32 %arg5, i1 %arg6) {
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; CHECK-LABEL: optspeed:
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; CHECK: // %bb.0: // %bb
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; CHECK-NEXT: stp x30, x23, [sp, #-48]! // 16-byte Folded Spill
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; CHECK-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w20, -16
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; CHECK-NEXT: .cfi_offset w21, -24
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; CHECK-NEXT: .cfi_offset w22, -32
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; CHECK-NEXT: .cfi_offset w23, -40
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; CHECK-NEXT: .cfi_offset w30, -48
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; CHECK-NEXT: mov w22, w5
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; CHECK-NEXT: mov x21, x4
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; CHECK-NEXT: mov x20, x3
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; CHECK-NEXT: mov x23, x2
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; CHECK-NEXT: mov w19, w1
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; CHECK-NEXT: b .LBB1_2
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; CHECK-NEXT: .LBB1_1: // %bb10
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: mov w0, w22
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; CHECK-NEXT: mov x1, x20
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; CHECK-NEXT: str wzr, [x21]
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; CHECK-NEXT: bl foo
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; CHECK-NEXT: .LBB1_2: // %bb8
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmp w19, #33
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; CHECK-NEXT: b.gt .LBB1_6
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; CHECK-NEXT: // %bb.3: // %bb8
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: cbz w19, .LBB1_2
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; CHECK-NEXT: // %bb.4: // %bb8
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: cmp w19, #10
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; CHECK-NEXT: b.ne .LBB1_2
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; CHECK-NEXT: // %bb.5: // %bb9
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: str wzr, [x23]
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; CHECK-NEXT: b .LBB1_2
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; CHECK-NEXT: .LBB1_6: // %bb8
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: cmp w19, #34
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; CHECK-NEXT: b.eq .LBB1_1
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; CHECK-NEXT: // %bb.7: // %bb8
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; CHECK-NEXT: // in Loop: Header=BB1_2 Depth=1
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; CHECK-NEXT: cmp w19, #39
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; CHECK-NEXT: b.eq .LBB1_1
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; CHECK-NEXT: b .LBB1_2
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bb:
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br label %bb7
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bb7: ; preds = %bb13, %bb
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%phi = phi i32 [ 0, %bb ], [ %spec.select, %bb13 ]
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br label %bb8
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bb8: ; preds = %bb10, %bb9, %bb8, %bb7
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switch i32 %arg1, label %bb8 [
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i32 10, label %bb9
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i32 1, label %bb16
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i32 0, label %bb13
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i32 39, label %bb10
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i32 34, label %bb10
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]
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bb9: ; preds = %bb8
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store i32 0, ptr %arg2, align 4
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br label %bb8
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bb10: ; preds = %bb8, %bb8
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store i32 0, ptr %arg4, align 4
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tail call void @foo(i32 %arg5, ptr %arg3)
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br label %bb8
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bb13: ; preds = %bb8
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%not.arg6 = xor i1 %arg6, true
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%spec.select = zext i1 %not.arg6 to i32
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br label %bb7
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bb16: ; preds = %bb8
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unreachable
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}
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