e6b4daf48c
Now, why would we want to do this? There are a small number of places where this works: 1. It helps peepholeopt when less flag checking. 2. It allows the folding of things such as x - 0x80000000 < 0 to be folded to cmp x, register holding this value 3. We can refine the other passes over time for this.
341 lines
9.3 KiB
LLVM
341 lines
9.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-none-elf %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64-none-elf -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define i32 @xori64i32(i64 %a) {
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; CHECK-LABEL: xori64i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: asr x8, x0, #63
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; CHECK-NEXT: eor w0, w8, #0x7fffffff
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; CHECK-NEXT: ret
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%shr4 = ashr i64 %a, 63
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%conv5 = trunc i64 %shr4 to i32
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%xor = xor i32 %conv5, 2147483647
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ret i32 %xor
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}
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define i64 @selecti64i64(i64 %a) {
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; CHECK-SD-LABEL: selecti64i64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr x8, x0, #63
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; CHECK-SD-NEXT: eor x0, x8, #0x7fffffff
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti64i64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov x8, #-2147483648 // =0xffffffff80000000
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; CHECK-GI-NEXT: mov w9, #2147483647 // =0x7fffffff
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; CHECK-GI-NEXT: cmp x0, #0
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; CHECK-GI-NEXT: csel x0, x9, x8, pl
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i64 %a, -1
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%s = select i1 %c, i64 2147483647, i64 -2147483648
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ret i64 %s
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}
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define i32 @selecti64i32(i64 %a) {
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; CHECK-SD-LABEL: selecti64i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr x8, x0, #63
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; CHECK-SD-NEXT: eor w0, w8, #0x7fffffff
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti64i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp x0, #0
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; CHECK-GI-NEXT: mov w9, #-2147483648 // =0x80000000
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; CHECK-GI-NEXT: cset w8, pl
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; CHECK-GI-NEXT: sbfx w8, w8, #0, #1
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; CHECK-GI-NEXT: add w0, w8, w9
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i64 %a, -1
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%s = select i1 %c, i32 2147483647, i32 -2147483648
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ret i32 %s
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}
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define i64 @selecti32i64(i32 %a) {
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; CHECK-SD-LABEL: selecti32i64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0
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; CHECK-SD-NEXT: sbfx x8, x0, #31, #1
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; CHECK-SD-NEXT: eor x0, x8, #0x7fffffff
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov x8, #-2147483648 // =0xffffffff80000000
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; CHECK-GI-NEXT: mov w9, #2147483647 // =0x7fffffff
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel x0, x9, x8, pl
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i64 2147483647, i64 -2147483648
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ret i64 %s
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}
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define i8 @xori32i8(i32 %a) {
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; CHECK-LABEL: xori32i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #84 // =0x54
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; CHECK-NEXT: eor w0, w8, w0, asr #31
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; CHECK-NEXT: ret
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%shr4 = ashr i32 %a, 31
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%conv5 = trunc i32 %shr4 to i8
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%xor = xor i8 %conv5, 84
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ret i8 %xor
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}
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define i32 @selecti32i32(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #84 // =0x54
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; CHECK-SD-NEXT: eor w0, w8, w0, asr #31
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #-85 // =0xffffffab
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; CHECK-GI-NEXT: mov w9, #84 // =0x54
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel w0, w9, w8, pl
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i32 84, i32 -85
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ret i32 %s
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}
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define i8 @selecti32i8(i32 %a) {
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; CHECK-SD-LABEL: selecti32i8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov w8, #84 // =0x54
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; CHECK-SD-NEXT: eor w0, w8, w0, asr #31
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #84 // =0x54
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; CHECK-GI-NEXT: mov w9, #-85 // =0xffffffab
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel w0, w8, w9, pl
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i8 84, i8 -85
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ret i8 %s
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}
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define i32 @selecti8i32(i8 %a) {
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; CHECK-SD-LABEL: selecti8i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sxtb w8, w0
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; CHECK-SD-NEXT: mov w9, #84 // =0x54
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; CHECK-SD-NEXT: eor w0, w9, w8, asr #7
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti8i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sxtb w8, w0
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; CHECK-GI-NEXT: mov w9, #-85 // =0xffffffab
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; CHECK-GI-NEXT: mov w10, #84 // =0x54
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; CHECK-GI-NEXT: cmp w8, #0
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; CHECK-GI-NEXT: csel w0, w10, w9, pl
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i8 %a, -1
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%s = select i1 %c, i32 84, i32 -85
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ret i32 %s
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}
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define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {
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; CHECK-SD-LABEL: icmpasreq:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csel w0, w1, w2, mi
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: icmpasreq:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
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; CHECK-GI-NEXT: cmp w8, w0, asr #31
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; CHECK-GI-NEXT: csel w0, w1, w2, eq
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; CHECK-GI-NEXT: ret
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%sh = ashr i32 %input, 31
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%c = icmp eq i32 %sh, -1
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%s = select i1 %c, i32 %a, i32 %b
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ret i32 %s
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}
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define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {
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; CHECK-SD-LABEL: icmpasrne:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmn w0, #1
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; CHECK-SD-NEXT: csel w0, w1, w2, gt
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: icmpasrne:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff
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; CHECK-GI-NEXT: cmp w8, w0, asr #31
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; CHECK-GI-NEXT: csel w0, w1, w2, ne
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; CHECK-GI-NEXT: ret
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%sh = ashr i32 %input, 31
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%c = icmp ne i32 %sh, -1
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%s = select i1 %c, i32 %a, i32 %b
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ret i32 %s
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}
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define i32 @selecti32i32_0(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32_0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr w0, w0, #31
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32_0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: cset w8, mi
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; CHECK-GI-NEXT: sbfx w0, w8, #0, #1
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i32 0, i32 -1
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ret i32 %s
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}
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define i32 @selecti32i32_m1(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32_m1:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mvn w8, w0
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; CHECK-SD-NEXT: asr w0, w8, #31
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32_m1:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: cset w8, pl
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; CHECK-GI-NEXT: sbfx w0, w8, #0, #1
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i32 -1, i32 0
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ret i32 %s
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}
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define i32 @selecti32i32_1(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32_1:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr w8, w0, #31
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; CHECK-SD-NEXT: eor w0, w8, #0x1
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32_1:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #-2 // =0xfffffffe
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csinc w0, w8, wzr, mi
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; CHECK-GI-NEXT: ret
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%c = icmp sgt i32 %a, -1
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%s = select i1 %c, i32 1, i32 -2
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ret i32 %s
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}
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define i32 @selecti32i32_sge(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32_sge:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr w8, w0, #31
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; CHECK-SD-NEXT: eor w0, w8, #0xc
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32_sge:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #-13 // =0xfffffff3
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; CHECK-GI-NEXT: mov w9, #12 // =0xc
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel w0, w9, w8, pl
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; CHECK-GI-NEXT: ret
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%c = icmp sge i32 %a, 0
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%s = select i1 %c, i32 12, i32 -13
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ret i32 %s
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}
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define i32 @selecti32i32_slt(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32_slt:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr w8, w0, #31
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; CHECK-SD-NEXT: eor w0, w8, #0xc
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32_slt:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #12 // =0xc
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; CHECK-GI-NEXT: mov w9, #-13 // =0xfffffff3
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel w0, w9, w8, mi
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; CHECK-GI-NEXT: ret
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%c = icmp slt i32 %a, 0
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%s = select i1 %c, i32 -13, i32 12
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ret i32 %s
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}
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define i32 @selecti32i32_sle(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32_sle:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr w8, w0, #31
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; CHECK-SD-NEXT: eor w0, w8, #0xc
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32_sle:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #12 // =0xc
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; CHECK-GI-NEXT: mov w9, #-13 // =0xfffffff3
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel w0, w9, w8, mi
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; CHECK-GI-NEXT: ret
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%c = icmp sle i32 %a, -1
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%s = select i1 %c, i32 -13, i32 12
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ret i32 %s
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}
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define i32 @selecti32i32_sgt(i32 %a) {
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; CHECK-SD-LABEL: selecti32i32_sgt:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr w8, w0, #31
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; CHECK-SD-NEXT: eor w0, w8, #0xc
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: selecti32i32_sgt:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #12 // =0xc
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; CHECK-GI-NEXT: mov w9, #-13 // =0xfffffff3
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel w0, w9, w8, mi
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; CHECK-GI-NEXT: ret
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%c = icmp sle i32 %a, -1
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%s = select i1 %c, i32 -13, i32 12
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ret i32 %s
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}
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define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {
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; CHECK-SD-LABEL: oneusecmp:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: asr w8, w0, #31
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; CHECK-SD-NEXT: cmp w0, #0
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; CHECK-SD-NEXT: csel w9, w2, w1, mi
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; CHECK-SD-NEXT: eor w8, w8, #0x7f
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; CHECK-SD-NEXT: add w0, w8, w9
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: oneusecmp:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mov w8, #127 // =0x7f
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; CHECK-GI-NEXT: mov w9, #-128 // =0xffffff80
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; CHECK-GI-NEXT: cmp w0, #0
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; CHECK-GI-NEXT: csel w8, w9, w8, mi
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; CHECK-GI-NEXT: csel w9, w2, w1, mi
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; CHECK-GI-NEXT: add w0, w8, w9
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; CHECK-GI-NEXT: ret
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%c = icmp sle i32 %a, -1
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%s = select i1 %c, i32 -128, i32 127
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%s2 = select i1 %c, i32 %d, i32 %b
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%x = add i32 %s, %s2
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ret i32 %x
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}
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