58a88001f3
This fixes the handling of subregister extract copies. This will allow AMDGPU to remove its implementation of shouldRewriteCopySrc, which exists as a 10 year old workaround to this bug. peephole-opt-fold-reg-sequence-subreg.mir will show the expected improvement once the custom implementation is removed. The copy coalescing processing here is overly abstracted from what's actually happening. Previously when visiting coalescable copy-like instructions, we would parse the sources one at a time and then pass the def of the root instruction into findNextSource. This means that the first thing the new ValueTracker constructed would do is getVRegDef to find the instruction we are currently processing. This adds an unnecessary step, placing a useless entry in the RewriteMap, and required skipping the no-op case where getNewSource would return the original source operand. This was a problem since in the case of a subregister extract, shouldRewriteCopySource would always say that it is useful to rewrite and the use-def chain walk would abort, returning the original operand. Move the process to start looking at the source operand to begin with. This does not fix the confused handling in the uncoalescable copy case which is proving to be more difficult. Some currently handled cases have multiple defs from a single source, and other handled cases have 0 input operands. It would be simpler if this was implemented with isCopyLikeInstr, rather than guessing at the operand structure as it does now. There are some improvements and some regressions. The regressions appear to be downstream issues for the most part. One of the uglier regressions is in PPC, where a sequence of insert_subrgs is used to build registers. I opened #125502 to use reg_sequence instead, which may help. The worst regression is an absurd SPARC testcase using a <251 x fp128>, which uses a very long chain of insert_subregs. We need improved subregister handling locally in PeepholeOptimizer, and other pasess like MachineCSE to fix some of the other regressions. We should handle subregister composes and folding more indexes into insert_subreg and reg_sequence.
119 lines
3.6 KiB
LLVM
119 lines
3.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; If we have a shift by sign-extended value, we can replace sign-extension
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; with zero-extension.
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define i32 @t0_shl(i32 %x, i8 %shamt) nounwind {
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; CHECK-LABEL: t0_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: lsl w0, w0, w8
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t1_lshr(i32 %x, i8 %shamt) nounwind {
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; CHECK-LABEL: t1_lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: lsr w0, w0, w8
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = lshr i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t2_ashr(i32 %x, i8 %shamt) nounwind {
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; CHECK-LABEL: t2_ashr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: asr w0, w0, w8
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = ashr i32 %x, %shamt_wide
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ret i32 %r
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}
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define <4 x i32> @t3_vec_shl(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t3_vec_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: shl v1.4s, v1.4s, #24
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; CHECK-NEXT: sshr v1.4s, v1.4s, #24
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = shl <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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define <4 x i32> @t4_vec_lshr(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t4_vec_lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: shl v1.4s, v1.4s, #24
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; CHECK-NEXT: sshr v1.4s, v1.4s, #24
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = lshr <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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define <4 x i32> @t5_vec_ashr(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t5_vec_ashr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: shl v1.4s, v1.4s, #24
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; CHECK-NEXT: sshr v1.4s, v1.4s, #24
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = ashr <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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; This is not valid for funnel shifts
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declare i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
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declare i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
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define i32 @n6_fshl(i32 %x, i32 %y, i8 %shamt) nounwind {
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; CHECK-LABEL: n6_fshl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsr w8, w1, #1
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; CHECK-NEXT: mvn w9, w2
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; CHECK-NEXT: lsl w10, w0, w2
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; CHECK-NEXT: lsr w8, w8, w9
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; CHECK-NEXT: orr w0, w10, w8
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %shamt_wide)
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ret i32 %r
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}
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define i32 @n7_fshr(i32 %x, i32 %y, i8 %shamt) nounwind {
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; CHECK-LABEL: n7_fshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl w8, w0, #1
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; CHECK-NEXT: mvn w9, w2
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; CHECK-NEXT: lsr w10, w1, w2
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; CHECK-NEXT: lsl w8, w8, w9
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; CHECK-NEXT: orr w0, w8, w10
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %shamt_wide)
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ret i32 %r
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}
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define i32 @n8_extrause(i32 %x, i8 %shamt, ptr %shamt_wide_store) nounwind {
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; CHECK-LABEL: n8_extrause:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: lsl w0, w0, w8
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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store i32 %shamt_wide, ptr %shamt_wide_store, align 4
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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