9828745661
The patch adds patterns to select the EXT_ZZI_CONSTRUCTIVE pseudo instead of the EXT_ZZI destructive instruction for vector_splice. This only works when the two inputs to vector_splice are identical. Given that registers aren't tied anymore, this gives the register allocator more freedom and a lot of MOVs get replaced with MOVPRFX. In some cases however, we could have just chosen the same input and output register, but regalloc preferred not to. This means we end up with some test cases now having more instructions: there is now a MOVPRFX while no MOV was previously needed.
53 lines
1.9 KiB
LLVM
53 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-linux-gnu"
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define <4 x i32> @test(ptr %arg1, ptr %arg2) {
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; CHECK-LABEL: test:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: mov x8, #8 // =0x8
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]
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; CHECK-NEXT: movprfx z0, z1
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; CHECK-NEXT: ext z0.b, z0.b, z1.b, #16
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; CHECK-NEXT: add z1.s, z1.s, z1.s
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; CHECK-NEXT: add z2.s, z2.s, z2.s
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; CHECK-NEXT: dup v0.4s, v0.s[2]
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; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
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; CHECK-NEXT: st1w { z2.s }, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i32>, ptr %arg1, align 256
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%1 = load <16 x i32>, ptr %arg2, align 256
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%shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <4 x i32> <i32 14, i32 14, i32 14, i32 14>
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%2 = add <16 x i32> %0, %0
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store <16 x i32> %2, ptr %arg1, align 256
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ret <4 x i32> %shvec
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}
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define <2 x i32> @test2(ptr %arg1, ptr %arg2) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: mov x8, #8 // =0x8
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-NEXT: ld1w { z2.s }, p0/z, [x0]
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; CHECK-NEXT: movprfx z0, z1
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; CHECK-NEXT: ext z0.b, z0.b, z1.b, #24
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; CHECK-NEXT: add z1.s, z1.s, z1.s
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; CHECK-NEXT: add z2.s, z2.s, z2.s
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; CHECK-NEXT: dup v0.2s, v0.s[0]
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; CHECK-NEXT: st1w { z1.s }, p0, [x0, x8, lsl #2]
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; CHECK-NEXT: st1w { z2.s }, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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%0 = load <16 x i32>, ptr %arg1, align 256
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%1 = load <16 x i32>, ptr %arg2, align 256
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%shvec = shufflevector <16 x i32> %0, <16 x i32> %1, <2 x i32> <i32 14, i32 14>
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%2 = add <16 x i32> %0, %0
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store <16 x i32> %2, ptr %arg1, align 256
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ret <2 x i32> %shvec
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}
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