af03d6b518
Similarly to #135016, refactor getPTrue to return splat (1) for all-active patterns. The main motivation for this is to improve code gen for fixed-length vector loads/stores that are converted to SVE masked memory ops when the vectors are wider than Neon. Emitting the mask as a splat helps DAGCombiner simplify all-active masked loads/stores into unmaked ones, for which it already has suitable combines and ISel has suitable patterns.
113 lines
3.1 KiB
LLVM
113 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=512 -aarch64-sve-vector-bits-max=512 < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define void @add_v64i8(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: add_v64i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ldr z1, [x1]
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; CHECK-NEXT: add z0.b, z0.b, z1.b
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <64 x i8>, ptr %a
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%op2 = load <64 x i8>, ptr %b
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%res = add <64 x i8> %op1, %op2
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store <64 x i8> %res, ptr %a
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ret void
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}
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define void @add_v32i16(ptr %a, ptr %b, ptr %c) #0 {
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; CHECK-LABEL: add_v32i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ldr z1, [x1]
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; CHECK-NEXT: add z0.h, z0.h, z1.h
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x i16>, ptr %a
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%op2 = load <32 x i16>, ptr %b
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%res = add <32 x i16> %op1, %op2
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store <32 x i16> %res, ptr %a
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ret void
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}
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define void @abs_v16i32(ptr %a) #0 {
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; CHECK-LABEL: abs_v16i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: abs z0.s, p0/m, z0.s
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x i32>, ptr %a
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%res = call <16 x i32> @llvm.abs.v16i32(<16 x i32> %op1, i1 false)
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store <16 x i32> %res, ptr %a
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ret void
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}
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define void @abs_v8i64(ptr %a) #0 {
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; CHECK-LABEL: abs_v8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: abs z0.d, p0/m, z0.d
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x i64>, ptr %a
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%res = call <8 x i64> @llvm.abs.v8i64(<8 x i64> %op1, i1 false)
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store <8 x i64> %res, ptr %a
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ret void
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}
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define void @fadd_v32f16(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fadd_v32f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ldr z1, [x1]
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; CHECK-NEXT: fadd z0.h, z0.h, z1.h
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <32 x half>, ptr %a
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%op2 = load <32 x half>, ptr %b
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%res = fadd <32 x half> %op1, %op2
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store <32 x half> %res, ptr %a
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ret void
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}
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define void @fadd_v16f32(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fadd_v16f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ldr z1, [x1]
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; CHECK-NEXT: fadd z0.s, z0.s, z1.s
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <16 x float>, ptr %a
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%op2 = load <16 x float>, ptr %b
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%res = fadd <16 x float> %op1, %op2
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store <16 x float> %res, ptr %a
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ret void
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}
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define void @fadd_v8f64(ptr %a, ptr %b) #0 {
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; CHECK-LABEL: fadd_v8f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: ldr z1, [x1]
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; CHECK-NEXT: fadd z0.d, z0.d, z1.d
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%op1 = load <8 x double>, ptr %a
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%op2 = load <8 x double>, ptr %b
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%res = fadd <8 x double> %op1, %op2
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store <8 x double> %res, ptr %a
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ret void
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}
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declare <16 x i32> @llvm.abs.v16i32(<16 x i32>, i1)
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declare <8 x i64> @llvm.abs.v8i64(<8 x i64>, i1)
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attributes #0 = { "target-features"="+sve" }
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