9828745661
The patch adds patterns to select the EXT_ZZI_CONSTRUCTIVE pseudo instead of the EXT_ZZI destructive instruction for vector_splice. This only works when the two inputs to vector_splice are identical. Given that registers aren't tied anymore, this gives the register allocator more freedom and a lot of MOVs get replaced with MOVPRFX. In some cases however, we could have just chosen the same input and output register, but regalloc preferred not to. This means we end up with some test cases now having more instructions: there is now a MOVPRFX while no MOV was previously needed.
94 lines
3.7 KiB
LLVM
94 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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; Currently there is no custom lowering for vector shuffles operating on types
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; bigger than NEON. However, having no support opens us up to a code generator
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; hang when expanding BUILD_VECTOR. Here we just validate the promblematic case
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; successfully exits code generation.
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define void @hang_when_merging_stores_after_legalisation(ptr %a, <2 x i32> %b) vscale_range(2,2) #0 {
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; CHECK-LABEL: hang_when_merging_stores_after_legalisation:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
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; CHECK-NEXT: mov z0.s, s0
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; CHECK-NEXT: movprfx z1, z0
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; CHECK-NEXT: ext z1.b, z1.b, z0.b, #16
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; CHECK-NEXT: st2 { v0.4s, v1.4s }, [x0]
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; CHECK-NEXT: ret
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%splat = shufflevector <2 x i32> %b, <2 x i32> poison, <8 x i32> zeroinitializer
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%interleaved.vec = shufflevector <8 x i32> %splat, <8 x i32> poison, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
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store <8 x i32> %interleaved.vec, ptr %a, align 4
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ret void
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}
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; Ensure we don't crash when trying to lower a shuffle via an extract
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define void @crash_when_lowering_extract_shuffle(ptr %dst, i1 %cond) vscale_range(2,2) #0 {
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; CHECK-LABEL: crash_when_lowering_extract_shuffle:
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; CHECK: // %bb.0:
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; CHECK-NEXT: tbnz w1, #0, .LBB1_2
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; CHECK-NEXT: // %bb.1: // %vector.body
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: movi v1.2d, #0000000000000000
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: umov w8, v0.b[8]
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; CHECK-NEXT: mov v1.b[1], v0.b[1]
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; CHECK-NEXT: movprfx z3, z0
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; CHECK-NEXT: ext z3.b, z3.b, z0.b, #16
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; CHECK-NEXT: ext v4.16b, v3.16b, v3.16b, #8
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; CHECK-NEXT: fmov s2, w8
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; CHECK-NEXT: mov v1.b[2], v0.b[2]
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; CHECK-NEXT: mov v2.b[1], v0.b[9]
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; CHECK-NEXT: mov v1.b[3], v0.b[3]
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; CHECK-NEXT: mov v2.b[2], v0.b[10]
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; CHECK-NEXT: mov v1.b[4], v0.b[4]
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; CHECK-NEXT: mov v2.b[3], v0.b[11]
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; CHECK-NEXT: mov v1.b[5], v0.b[5]
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; CHECK-NEXT: mov v2.b[4], v0.b[12]
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; CHECK-NEXT: mov v1.b[6], v0.b[6]
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; CHECK-NEXT: mov v2.b[5], v0.b[13]
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; CHECK-NEXT: mov v1.b[7], v0.b[7]
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; CHECK-NEXT: mov v2.b[6], v0.b[14]
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; CHECK-NEXT: uunpklo z1.h, z1.b
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; CHECK-NEXT: mov v2.b[7], v0.b[15]
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; CHECK-NEXT: uunpklo z0.h, z3.b
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; CHECK-NEXT: uunpklo z3.h, z4.b
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; CHECK-NEXT: uunpklo z1.s, z1.h
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; CHECK-NEXT: uunpklo z2.h, z2.b
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; CHECK-NEXT: uunpklo z0.s, z0.h
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; CHECK-NEXT: uunpklo z3.s, z3.h
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; CHECK-NEXT: lsl z1.s, z1.s, #31
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; CHECK-NEXT: uunpklo z2.s, z2.h
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; CHECK-NEXT: lsl z0.s, z0.s, #31
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; CHECK-NEXT: lsl z3.s, z3.s, #31
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; CHECK-NEXT: asr z1.s, z1.s, #31
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; CHECK-NEXT: asr z0.s, z0.s, #31
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; CHECK-NEXT: asr z3.s, z3.s, #31
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; CHECK-NEXT: lsl z2.s, z2.s, #31
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; CHECK-NEXT: cmpne p3.s, p0/z, z1.s, #0
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; CHECK-NEXT: cmpne p1.s, p0/z, z0.s, #0
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; CHECK-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NEXT: cmpne p2.s, p0/z, z3.s, #0
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; CHECK-NEXT: asr z2.s, z2.s, #31
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; CHECK-NEXT: cmpne p0.s, p0/z, z2.s, #0
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; CHECK-NEXT: st1w { z0.s }, p1, [x0, #2, mul vl]
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; CHECK-NEXT: st1w { z0.s }, p2, [x0, #3, mul vl]
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; CHECK-NEXT: st1w { z0.s }, p3, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x0, #1, mul vl]
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; CHECK-NEXT: .LBB1_2: // %exit
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; CHECK-NEXT: ret
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%broadcast.splat = shufflevector <32 x i1> zeroinitializer, <32 x i1> zeroinitializer, <32 x i32> zeroinitializer
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br i1 %cond, label %exit, label %vector.body
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vector.body:
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%1 = load <32 x i32>, ptr %dst, align 16
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%predphi = select <32 x i1> %broadcast.splat, <32 x i32> zeroinitializer, <32 x i32> %1
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store <32 x i32> %predphi, ptr %dst, align 16
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br label %exit
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exit:
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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