15fbdc2b96
Currently, given:
```cpp
svuint8_t foo(uint8_t *x) {
return svld1(svptrue_b8(), x);
}
```
We generate:
```gas
foo:
ptrue p0.b
ld1b { z0.b }, p0/z, [x0]
ret
```
However, on little-endian and with unaligned memory accesses allowed, we
could instead be using LDR as follows:
```gas
foo:
ldr z0, [x0]
ret
```
The second form avoids the predicate dependency.
Likewise for other types and stores.
93 lines
3.0 KiB
LLVM
93 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck --check-prefix CHECK-NO-STRICT-ALIGN %s
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+strict-align < %s | FileCheck %s
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define void @nxv16i8(ptr %ldptr, ptr %stptr) {
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; CHECK-NO-STRICT-ALIGN-LABEL: nxv16i8:
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; CHECK-NO-STRICT-ALIGN: // %bb.0:
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; CHECK-NO-STRICT-ALIGN-NEXT: ldr z0, [x0]
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; CHECK-NO-STRICT-ALIGN-NEXT: str z0, [x1]
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; CHECK-NO-STRICT-ALIGN-NEXT: ret
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;
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; CHECK-LABEL: nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: ld1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: st1b { z0.b }, p0, [x1]
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; CHECK-NEXT: ret
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%l3 = load <vscale x 16 x i8>, ptr %ldptr, align 1
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store <vscale x 16 x i8> %l3, ptr %stptr, align 1
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ret void
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}
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define void @nxv8i16(ptr %ldptr, ptr %stptr) {
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; CHECK-NO-STRICT-ALIGN-LABEL: nxv8i16:
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; CHECK-NO-STRICT-ALIGN: // %bb.0:
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; CHECK-NO-STRICT-ALIGN-NEXT: ldr z0, [x0]
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; CHECK-NO-STRICT-ALIGN-NEXT: str z0, [x1]
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; CHECK-NO-STRICT-ALIGN-NEXT: ret
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;
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; CHECK-LABEL: nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: st1h { z0.h }, p0, [x1]
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; CHECK-NEXT: ret
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%l3 = load <vscale x 8 x i16>, ptr %ldptr, align 2
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store <vscale x 8 x i16> %l3, ptr %stptr, align 2
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ret void
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}
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define void @nxv4i32(ptr %ldptr, ptr %stptr) {
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; CHECK-NO-STRICT-ALIGN-LABEL: nxv4i32:
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; CHECK-NO-STRICT-ALIGN: // %bb.0:
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; CHECK-NO-STRICT-ALIGN-NEXT: ldr z0, [x0]
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; CHECK-NO-STRICT-ALIGN-NEXT: str z0, [x1]
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; CHECK-NO-STRICT-ALIGN-NEXT: ret
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;
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; CHECK-LABEL: nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.s }, p0, [x1]
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; CHECK-NEXT: ret
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%l3 = load <vscale x 4 x i32>, ptr %ldptr, align 4
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store <vscale x 4 x i32> %l3, ptr %stptr, align 4
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ret void
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}
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define void @nxv2i64(ptr %ldptr, ptr %stptr) {
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; CHECK-NO-STRICT-ALIGN-LABEL: nxv2i64:
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; CHECK-NO-STRICT-ALIGN: // %bb.0:
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; CHECK-NO-STRICT-ALIGN-NEXT: ldr z0, [x0]
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; CHECK-NO-STRICT-ALIGN-NEXT: str z0, [x1]
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; CHECK-NO-STRICT-ALIGN-NEXT: ret
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;
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; CHECK-LABEL: nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1d { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%l3 = load <vscale x 2 x i64>, ptr %ldptr, align 8
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store <vscale x 2 x i64> %l3, ptr %stptr, align 8
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ret void
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}
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define void @nxv16i1(ptr %ldptr, ptr %stptr) {
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; CHECK-NO-STRICT-ALIGN-LABEL: nxv16i1:
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; CHECK-NO-STRICT-ALIGN: // %bb.0:
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; CHECK-NO-STRICT-ALIGN-NEXT: ldr p0, [x0]
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; CHECK-NO-STRICT-ALIGN-NEXT: str p0, [x1]
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; CHECK-NO-STRICT-ALIGN-NEXT: ret
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;
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; CHECK-LABEL: nxv16i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr p0, [x0]
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; CHECK-NEXT: str p0, [x1]
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; CHECK-NEXT: ret
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%l3 = load <vscale x 16 x i1>, ptr %ldptr, align 2
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store <vscale x 16 x i1> %l3, ptr %stptr, align 2
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ret void
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}
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