db158c7c83
Refresh of the generic scheduling model to use A510 instead of A55. Main benefits are to the little core, and introducing SVE scheduling information. Changes tested on various OoO cores, no performance degradation is seen. Differential Revision: https://reviews.llvm.org/D156799
127 lines
3.4 KiB
LLVM
127 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; ANDV
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define i1 @andv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: andv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: nots p0.b, p2/z, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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define i1 @andv_nxv64i1(<vscale x 64 x i1> %a) {
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; CHECK-LABEL: andv_nxv64i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and p1.b, p1/z, p1.b, p3.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ptrue p1.b
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; CHECK-NEXT: nots p0.b, p1/z, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1> %a)
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ret i1 %res
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}
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; ORV
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define i1 @orv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: orv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; XORV
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define i1 @xorv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: xorv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: eor p0.b, p2/z, p0.b, p1.b
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; CHECK-NEXT: cntp x8, p2, p0.b
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; CHECK-NEXT: and w0, w8, #0x1
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; SMAXV
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define i1 @smaxv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: smaxv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: nots p0.b, p2/z, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; SMINV
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define i1 @sminv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: sminv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; UMAXV
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define i1 @umaxv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: umaxv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sel p0.b, p0, p0.b, p1.b
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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; UMINV
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define i1 @uminv_nxv32i1(<vscale x 32 x i1> %a) {
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; CHECK-LABEL: uminv_nxv32i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: nots p0.b, p2/z, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%res = call i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1> %a)
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ret i1 %res
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}
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declare i1 @llvm.vector.reduce.and.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.and.nxv64i1(<vscale x 64 x i1>)
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declare i1 @llvm.vector.reduce.or.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.smax.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.smin.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.umax.nxv32i1(<vscale x 32 x i1>)
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declare i1 @llvm.vector.reduce.umin.nxv32i1(<vscale x 32 x i1>)
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